drivers/gpu/drm/vc4/vc4_dpi.c

36

# define DPI_ORDER_MASK VC4_MASK(15, 14)

drivers/gpu/drm/vc4/vc4_dpi.c

46

# define DPI_FORMAT_MASK VC4_MASK(13, 11)

drivers/gpu/drm/vc4/vc4_dsi.c

101

# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

113

# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

116

# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_dsi.c

118

# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

120

# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

129

# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

131

# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

138

# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)

drivers/gpu/drm/vc4/vc4_dsi.c

140

# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)

drivers/gpu/drm/vc4/vc4_dsi.c

156

# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)

drivers/gpu/drm/vc4/vc4_dsi.c

160

# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_dsi.c

173

# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)

drivers/gpu/drm/vc4/vc4_dsi.c

188

# define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)

drivers/gpu/drm/vc4/vc4_dsi.c

295

# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)

drivers/gpu/drm/vc4/vc4_dsi.c

298

# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)

drivers/gpu/drm/vc4/vc4_dsi.c

328

# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)

drivers/gpu/drm/vc4/vc4_dsi.c

330

# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)

drivers/gpu/drm/vc4/vc4_dsi.c

332

# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)

drivers/gpu/drm/vc4/vc4_dsi.c

334

# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)

drivers/gpu/drm/vc4/vc4_dsi.c

336

# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)

drivers/gpu/drm/vc4/vc4_dsi.c

338

# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)

drivers/gpu/drm/vc4/vc4_dsi.c

340

# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)

drivers/gpu/drm/vc4/vc4_dsi.c

342

# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_dsi.c

357

# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_dsi.c

359

# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

363

# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

365

# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)

drivers/gpu/drm/vc4/vc4_dsi.c

367

# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

376

# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)

drivers/gpu/drm/vc4/vc4_dsi.c

464

# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)

drivers/gpu/drm/vc4/vc4_dsi.c

466

# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)

drivers/gpu/drm/vc4/vc4_dsi.c

468

# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

472

# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)

drivers/gpu/drm/vc4/vc4_dsi.c

474

# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

478

# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

482

# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)

drivers/gpu/drm/vc4/vc4_dsi.c

484

# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)

drivers/gpu/drm/vc4/vc4_dsi.c

486

# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

490

# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)

drivers/gpu/drm/vc4/vc4_dsi.c

492

# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)

drivers/gpu/drm/vc4/vc4_dsi.c

494

# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

498

# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

502

# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_dsi.c

504

# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_dsi.c

506

# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

508

# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

512

# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

518

# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)

drivers/gpu/drm/vc4/vc4_dsi.c

520

# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_dsi.c

522

# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

524

# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_dsi.c

526

# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_dsi.c

55

# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_dsi.c

57

# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)

drivers/gpu/drm/vc4/vc4_dsi.c

60

# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)

drivers/gpu/drm/vc4/vc4_dsi.c

73

# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)

drivers/gpu/drm/vc4/vc4_dsi.c

76

# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)

drivers/gpu/drm/vc4/vc4_dsi.c

97

# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_dsi.c

99

# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)

drivers/gpu/drm/vc4/vc4_hdmi.c

104

#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_hdmi.c

106

#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

67

#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_hdmi.c

71

#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

74

#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)

drivers/gpu/drm/vc4/vc4_hdmi.c

76

#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

79

#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)

drivers/gpu/drm/vc4/vc4_hdmi.c

81

#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)

drivers/gpu/drm/vc4/vc4_hdmi.c

83

#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

86

#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)

drivers/gpu/drm/vc4/vc4_hdmi.c

89

#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

91

#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_hdmi.c

96

#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)

drivers/gpu/drm/vc4/vc4_hdmi.c

99

#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

101

#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK VC4_MASK(5, 4)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

103

#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK VC4_MASK(1, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

106

#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK VC4_MASK(27, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

109

#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK VC4_MASK(27, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

112

#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

114

#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

123

#define VC4_HDMI_RM_OFFSET_OFFSET_MASK VC4_MASK(30, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

126

#define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

138

#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

140

#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

141

#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

144

#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

146

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL_MASK VC4_MASK(31, 28)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

147

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE_MASK VC4_MASK(27, 27)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

148

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL_MASK VC4_MASK(26, 26)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

149

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN_MASK VC4_MASK(25, 25)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

150

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL_MASK VC4_MASK(24, 23)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

151

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN_MASK VC4_MASK(22, 22)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

152

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL_MASK VC4_MASK(21, 21)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

153

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN_MASK VC4_MASK(20, 20)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

154

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL_MASK VC4_MASK(19, 18)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

155

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN_MASK VC4_MASK(17, 17)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

156

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN_MASK VC4_MASK(16, 16)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

157

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

158

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN_MASK VC4_MASK(11, 11)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

159

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT_MASK VC4_MASK(10, 8)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

160

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT_MASK VC4_MASK(7, 5)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

161

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING_MASK VC4_MASK(4, 3)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

162

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING_MASK VC4_MASK(2, 1)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

163

#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN_MASK VC4_MASK(0, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

23

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

25

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

27

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

29

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

31

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

33

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

35

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

37

#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

40

#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

42

#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(14, 10)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

44

#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_MASK VC4_MASK(9, 5)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

46

#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

49

#define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_MASK VC4_MASK(19, 16)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

51

#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

53

#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_MASK VC4_MASK(11, 8)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

55

#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

57

#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

60

#define VC4_HDMI_TX_PHY_CTL_3_RP_MASK VC4_MASK(19, 17)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

62

#define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK VC4_MASK(16, 12)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

64

#define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK VC4_MASK(11, 10)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

66

#define VC4_HDMI_TX_PHY_CTL_3_CP_MASK VC4_MASK(9, 8)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

68

#define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK VC4_MASK(7, 6)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

70

#define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

77

#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_MASK VC4_MASK(9, 9)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

84

#define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_MASK VC4_MASK(27, 16)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

86

#define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_MASK VC4_MASK(15, 14)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

89

#define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_MASK VC4_MASK(12, 11)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

92

#define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

95

#define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

97

#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_MASK VC4_MASK(13, 12)

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

99

#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_MASK VC4_MASK(9, 8)

drivers/gpu/drm/vc4/vc4_packet.h

183

#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)

drivers/gpu/drm/vc4/vc4_packet.h

195

#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)

drivers/gpu/drm/vc4/vc4_packet.h

202

#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)

drivers/gpu/drm/vc4/vc4_packet.h

205

#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)

drivers/gpu/drm/vc4/vc4_packet.h

258

#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5)

drivers/gpu/drm/vc4/vc4_packet.h

265

#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3)

drivers/gpu/drm/vc4/vc4_packet.h

285

#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)

drivers/gpu/drm/vc4/vc4_packet.h

292

#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_packet.h

329

#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12)

drivers/gpu/drm/vc4/vc4_packet.h

331

#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10)

drivers/gpu/drm/vc4/vc4_packet.h

333

#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9)

drivers/gpu/drm/vc4/vc4_packet.h

335

#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8)

drivers/gpu/drm/vc4/vc4_packet.h

337

#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_packet.h

339

#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_packet.h

342

#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31)

drivers/gpu/drm/vc4/vc4_packet.h

344

#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20)

drivers/gpu/drm/vc4/vc4_packet.h

346

#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19)

drivers/gpu/drm/vc4/vc4_packet.h

348

#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8)

drivers/gpu/drm/vc4/vc4_packet.h

351

#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7)

drivers/gpu/drm/vc4/vc4_packet.h

356

#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4)

drivers/gpu/drm/vc4/vc4_packet.h

365

#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_packet.h

367

#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0)

drivers/gpu/drm/vc4/vc4_packet.h

374

#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_packet.h

382

#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12)

drivers/gpu/drm/vc4/vc4_packet.h

384

#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0)

drivers/gpu/drm/vc4/vc4_packet.h

388

#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12)

drivers/gpu/drm/vc4/vc4_packet.h

390

#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0)

drivers/gpu/drm/vc4/vc4_packet.h

394

#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12)

drivers/gpu/drm/vc4/vc4_packet.h

396

#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1002

# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1004

# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1017

# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)

drivers/gpu/drm/vc4/vc4_regs.h

1026

# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_regs.h

1036

VC4_MASK(5, 4)

drivers/gpu/drm/vc4/vc4_regs.h

1041

# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1044

VC4_MASK(7, 6)

drivers/gpu/drm/vc4/vc4_regs.h

1051

VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_regs.h

1108

#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)

drivers/gpu/drm/vc4/vc4_regs.h

1111

#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)

drivers/gpu/drm/vc4/vc4_regs.h

1122

#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)

drivers/gpu/drm/vc4/vc4_regs.h

1129

#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)

drivers/gpu/drm/vc4/vc4_regs.h

1132

#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)

drivers/gpu/drm/vc4/vc4_regs.h

1143

#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1146

#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)

drivers/gpu/drm/vc4/vc4_regs.h

1162

#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1165

#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1167

#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_regs.h

1170

#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)

drivers/gpu/drm/vc4/vc4_regs.h

1173

#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1176

#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1179

#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1185

#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

1198

#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)

drivers/gpu/drm/vc4/vc4_regs.h

1203

#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)

drivers/gpu/drm/vc4/vc4_regs.h

1207

#define SCALER6D_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(22, 20)

drivers/gpu/drm/vc4/vc4_regs.h

1209

#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1212

#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1215

#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1218

#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1221

#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

1230

#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1233

#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1236

#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1239

#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1247

#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_regs.h

1250

#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1253

#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1256

#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1266

#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)

drivers/gpu/drm/vc4/vc4_regs.h

1269

#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)

drivers/gpu/drm/vc4/vc4_regs.h

1272

#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)

drivers/gpu/drm/vc4/vc4_regs.h

1275

#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1285

#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)

drivers/gpu/drm/vc4/vc4_regs.h

1288

#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

1291

#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

1301

#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1303

#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1305

#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1316

#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1318

#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1321

#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1326

#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1330

#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1332

#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1336

#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)

drivers/gpu/drm/vc4/vc4_regs.h

1340

#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1345

#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1347

#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1352

#define SCALER6_CTL0_NEXT_MASK VC4_MASK(29, 24)

drivers/gpu/drm/vc4/vc4_regs.h

1354

#define SCALER6_CTL0_ADDR_MODE_MASK VC4_MASK(22, 20)

drivers/gpu/drm/vc4/vc4_regs.h

1361

#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)

drivers/gpu/drm/vc4/vc4_regs.h

1365

#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)

drivers/gpu/drm/vc4/vc4_regs.h

1366

#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1367

#define SCALER6_CTL0_SCL0_MODE_MASK VC4_MASK(7, 5)

drivers/gpu/drm/vc4/vc4_regs.h

1368

#define SCALER6_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1370

#define SCALER6_POS0_START_Y_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1372

#define SCALER6_POS0_START_X_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1374

#define SCALER6_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

1379

#define SCALER6C_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1380

#define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4)

drivers/gpu/drm/vc4/vc4_regs.h

1382

#define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1383

#define SCALER6_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1385

#define SCALER6_POS2_SRC_LINES_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1386

#define SCALER6_POS2_SRC_WIDTH_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1389

#define SCALER6_PTR0_UPM_BASE_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

1390

#define SCALER6_PTR0_UPM_HANDLE_MASK VC4_MASK(14, 10)

drivers/gpu/drm/vc4/vc4_regs.h

1391

#define SCALER6_PTR0_UPM_BUFF_SIZE_MASK VC4_MASK(9, 8)

drivers/gpu/drm/vc4/vc4_regs.h

1396

#define SCALER6_PTR0_UPPER_ADDR_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1398

#define SCALER6_PTR2_ALPHA_BPP_MASK VC4_MASK(31, 31)

drivers/gpu/drm/vc4/vc4_regs.h

1401

#define SCALER6_PTR2_ALPHA_ORDER_MASK VC4_MASK(30, 30)

drivers/gpu/drm/vc4/vc4_regs.h

1404

#define SCALER6_PTR2_ALPHA_OFFS_MASK VC4_MASK(29, 27)

drivers/gpu/drm/vc4/vc4_regs.h

1405

#define SCALER6_PTR2_LSKIP_MASK VC4_MASK(26, 24)

drivers/gpu/drm/vc4/vc4_regs.h

1406

#define SCALER6_PTR2_PITCH_MASK VC4_MASK(16, 0)

drivers/gpu/drm/vc4/vc4_regs.h

1407

#define SCALER6_PTR2_FETCH_COUNT_MASK VC4_MASK(26, 16)

drivers/gpu/drm/vc4/vc4_regs.h

146

# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)

drivers/gpu/drm/vc4/vc4_regs.h

148

# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)

drivers/gpu/drm/vc4/vc4_regs.h

156

# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)

drivers/gpu/drm/vc4/vc4_regs.h

161

# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)

drivers/gpu/drm/vc4/vc4_regs.h

166

# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)

drivers/gpu/drm/vc4/vc4_regs.h

173

# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)

drivers/gpu/drm/vc4/vc4_regs.h

185

# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

187

# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

191

# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

193

# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

197

# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

199

# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

203

# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

205

# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

229

# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)

drivers/gpu/drm/vc4/vc4_regs.h

234

# define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8)

drivers/gpu/drm/vc4/vc4_regs.h

235

# define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_regs.h

243

# define SCALER_DISPCTRL_PANIC0_MASK VC4_MASK(25, 24)

drivers/gpu/drm/vc4/vc4_regs.h

245

# define SCALER_DISPCTRL_PANIC1_MASK VC4_MASK(27, 26)

drivers/gpu/drm/vc4/vc4_regs.h

247

# define SCALER_DISPCTRL_PANIC2_MASK VC4_MASK(29, 28)

drivers/gpu/drm/vc4/vc4_regs.h

249

# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)

drivers/gpu/drm/vc4/vc4_regs.h

281

# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)

drivers/gpu/drm/vc4/vc4_regs.h

306

# define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \

drivers/gpu/drm/vc4/vc4_regs.h

329

# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)

drivers/gpu/drm/vc4/vc4_regs.h

335

# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

339

# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

374

# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)

drivers/gpu/drm/vc4/vc4_regs.h

376

# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

379

# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

388

# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)

drivers/gpu/drm/vc4/vc4_regs.h

390

# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

398

# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)

drivers/gpu/drm/vc4/vc4_regs.h

407

# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)

drivers/gpu/drm/vc4/vc4_regs.h

415

# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

423

# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

428

# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

437

# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)

drivers/gpu/drm/vc4/vc4_regs.h

439

# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)

drivers/gpu/drm/vc4/vc4_regs.h

441

# define SCALER5_DISPSTAT1_FRCNT0_MASK VC4_MASK(25, 20)

drivers/gpu/drm/vc4/vc4_regs.h

443

# define SCALER5_DISPSTAT1_FRCNT1_MASK VC4_MASK(19, 14)

drivers/gpu/drm/vc4/vc4_regs.h

45

# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)

drivers/gpu/drm/vc4/vc4_regs.h

461

# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)

drivers/gpu/drm/vc4/vc4_regs.h

463

# define SCALER5_DISPSTAT2_FRCNT2_MASK VC4_MASK(19, 14)

drivers/gpu/drm/vc4/vc4_regs.h

47

# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

480

# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)

drivers/gpu/drm/vc4/vc4_regs.h

488

# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

49

# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_regs.h

490

# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

492

# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

497

# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)

drivers/gpu/drm/vc4/vc4_regs.h

499

# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

501

# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_regs.h

505

# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)

drivers/gpu/drm/vc4/vc4_regs.h

507

# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

509

# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_regs.h

51

# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)

drivers/gpu/drm/vc4/vc4_regs.h

513

# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)

drivers/gpu/drm/vc4/vc4_regs.h

515

# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

517

# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_regs.h

53

# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_regs.h

534

# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)

drivers/gpu/drm/vc4/vc4_regs.h

544

# define SCALER6_VERSION_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

55

# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_regs.h

555

# define SCALER6_CONTROL_PF_LINES_MASK VC4_MASK(22, 18)

drivers/gpu/drm/vc4/vc4_regs.h

557

# define SCALER6_CONTROL_DSP1_TARGET_MASK VC4_MASK(13, 12)

drivers/gpu/drm/vc4/vc4_regs.h

558

# define SCALER6_CONTROL_MAX_REQS_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_regs.h

570

# define SCALER6_DISPX_CTRL0_FWIDTH_MASK VC4_MASK(28, 16)

drivers/gpu/drm/vc4/vc4_regs.h

572

# define SCALER6_DISPX_CTRL0_ONECTX_MASK VC4_MASK(14, 13)

drivers/gpu/drm/vc4/vc4_regs.h

573

# define SCALER6_DISPX_CTRL0_LINES_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

591

# define SCALER6_DISPX_LPTRS_HEADE_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

597

# define SCALER6_DISPX_COB_TOP_MASK VC4_MASK(31, 16)

drivers/gpu/drm/vc4/vc4_regs.h

598

# define SCALER6_DISPX_COB_BASE_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

605

# define SCALER6_DISPX_STATUS_FRCNT_MASK VC4_MASK(21, 16)

drivers/gpu/drm/vc4/vc4_regs.h

607

# define SCALER6_DISPX_STATUS_MODE_MASK VC4_MASK(14, 13)

drivers/gpu/drm/vc4/vc4_regs.h

612

# define SCALER6_DISPX_STATUS_YLINE_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

619

# define SCALER6_DISPX_DL_LACT_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

66

# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)

drivers/gpu/drm/vc4/vc4_regs.h

68

# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)

drivers/gpu/drm/vc4/vc4_regs.h

70

# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)

drivers/gpu/drm/vc4/vc4_regs.h

72

# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)

drivers/gpu/drm/vc4/vc4_regs.h

750

# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)

drivers/gpu/drm/vc4/vc4_regs.h

757

# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)

drivers/gpu/drm/vc4/vc4_regs.h

763

# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

766

# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

774

# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

808

# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)

drivers/gpu/drm/vc4/vc4_regs.h

814

# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

818

# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)

drivers/gpu/drm/vc4/vc4_regs.h

821

# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)

drivers/gpu/drm/vc4/vc4_regs.h

824

# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)

drivers/gpu/drm/vc4/vc4_regs.h

846

# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)

drivers/gpu/drm/vc4/vc4_regs.h

849

# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)

drivers/gpu/drm/vc4/vc4_regs.h

852

# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)

drivers/gpu/drm/vc4/vc4_regs.h

856

# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)

drivers/gpu/drm/vc4/vc4_regs.h

859

# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)

drivers/gpu/drm/vc4/vc4_regs.h

872

# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)

drivers/gpu/drm/vc4/vc4_regs.h

889

# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)

drivers/gpu/drm/vc4/vc4_regs.h

892

# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)

drivers/gpu/drm/vc4/vc4_regs.h

896

# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)

drivers/gpu/drm/vc4/vc4_regs.h

902

# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)

drivers/gpu/drm/vc4/vc4_regs.h

904

# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)

drivers/gpu/drm/vc4/vc4_regs.h

906

# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)

drivers/gpu/drm/vc4/vc4_regs.h

908

# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)

drivers/gpu/drm/vc4/vc4_regs.h

910

# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)

drivers/gpu/drm/vc4/vc4_regs.h

913

# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_regs.h

915

# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

917

# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

919

# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

922

# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)

drivers/gpu/drm/vc4/vc4_regs.h

924

# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)

drivers/gpu/drm/vc4/vc4_regs.h

926

# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

928

# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

936

# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)

drivers/gpu/drm/vc4/vc4_regs.h

938

# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)

drivers/gpu/drm/vc4/vc4_regs.h

940

# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)

drivers/gpu/drm/vc4/vc4_regs.h

971

# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)

drivers/gpu/drm/vc4/vc4_regs.h

981

# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)

drivers/gpu/drm/vc4/vc4_regs.h

983

# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)

drivers/gpu/drm/vc4/vc4_regs.h

985

# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)

drivers/gpu/drm/vc4/vc4_regs.h

987

# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)

drivers/gpu/drm/vc4/vc4_regs.h

990

# define VC6_D_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 23)

drivers/gpu/drm/vc4/vc4_regs.h

992

# define VC6_D_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 15)

drivers/gpu/drm/vc4/vc4_regs.h

994

# define VC6_D_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 7)

drivers/gpu/drm/vc4/vc4_regs.h

996

# define VC6_D_HD_MAI_THR_DREQLOW_MASK VC4_MASK(6, 0)