drivers/gpu/drm/vc4/vc4_crtc.c

100

base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;

drivers/gpu/drm/vc4/vc4_crtc.c

148

*vpos = VC4_GET_FIELD(val, SCALER6_DISPX_STATUS_YLINE);

drivers/gpu/drm/vc4/vc4_crtc.c

150

*vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);

drivers/gpu/drm/vc4/vc4_crtc.c

582

encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);

drivers/gpu/drm/vc4/vc4_crtc.c

836

current_dlist = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_DL(chan)),

drivers/gpu/drm/vc4/vc4_crtc.c

95

top = VC4_GET_FIELD(dispbase, SCALER6_DISPX_COB_TOP) & ~3;

drivers/gpu/drm/vc4/vc4_crtc.c

96

base = VC4_GET_FIELD(dispbase, SCALER6_DISPX_COB_BASE) & ~3;

drivers/gpu/drm/vc4/vc4_crtc.c

99

top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;

drivers/gpu/drm/vc4/vc4_dsi.c

1304

u32 rxlen = VC4_GET_FIELD(rxpkt1h,

drivers/gpu/drm/vc4/vc4_dsi.c

1319

msg_rx[0] = VC4_GET_FIELD(rxpkt1h,

drivers/gpu/drm/vc4/vc4_dsi.c

1322

msg_rx[1] = VC4_GET_FIELD(rxpkt1h,

drivers/gpu/drm/vc4/vc4_hvs.c

1654

if (VC4_GET_FIELD(HVS_READ(SCALER6_VERSION), SCALER6_VERSION) ==

drivers/gpu/drm/vc4/vc4_hvs.c

254

dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)),

drivers/gpu/drm/vc4/vc4_hvs.c

274

VC4_GET_FIELD(dlist_word,

drivers/gpu/drm/vc4/vc4_hvs.c

298

dispstat = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(i)),

drivers/gpu/drm/vc4/vc4_hvs.c

308

active_dlist = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_DL(i)),

drivers/gpu/drm/vc4/vc4_hvs.c

323

VC4_GET_FIELD(dlist_word,

drivers/gpu/drm/vc4/vc4_hvs.c

489

field = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(fifo)),

drivers/gpu/drm/vc4/vc4_hvs.c

495

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),

drivers/gpu/drm/vc4/vc4_hvs.c

499

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),

drivers/gpu/drm/vc4/vc4_hvs.c

503

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),

drivers/gpu/drm/vc4/vc4_hvs.c

511

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),

drivers/gpu/drm/vc4/vc4_hvs.c

515

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),

drivers/gpu/drm/vc4/vc4_hvs.c

519

field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),

drivers/gpu/drm/vc4/vc4_hvs.c

740

WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),

drivers/gpu/drm/vc4/vc4_hvs.c

772

WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(chan)),

drivers/gpu/drm/vc4/vc4_kms.c

286

VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL),

drivers/gpu/drm/vc4/vc4_render_cl.c

441

uint8_t tiling = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

443

uint8_t buffer = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

445

uint8_t format = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

540

uint8_t tiling = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_render_cl.c

542

uint8_t format = VC4_GET_FIELD(surf->bits,

drivers/gpu/drm/vc4/vc4_v3d.c

108

uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);

drivers/gpu/drm/vc4/vc4_v3d.c

109

uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);

drivers/gpu/drm/vc4/vc4_v3d.c

110

uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);

drivers/gpu/drm/vc4/vc4_v3d.c

113

VC4_GET_FIELD(ident1, V3D_IDENT1_REV));

drivers/gpu/drm/vc4/vc4_v3d.c

118

VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));

drivers/gpu/drm/vc4/vc4_validate.c

585

uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS);

drivers/gpu/drm/vc4/vc4_validate.c

586

uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH);

drivers/gpu/drm/vc4/vc4_validate.c

587

uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT);

drivers/gpu/drm/vc4/vc4_validate.c

619

if (VC4_GET_FIELD(p2, VC4_TEX_P2_PTYPE) ==

drivers/gpu/drm/vc4/vc4_validate.c

622

if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) ==

drivers/gpu/drm/vc4/vc4_validate.c

637

type = (VC4_GET_FIELD(p0, VC4_TEX_P0_TYPE) |

drivers/gpu/drm/vc4/vc4_validate.c

638

(VC4_GET_FIELD(p1, VC4_TEX_P1_TYPE4) << 4));