VG_NUM_DPPCLK_DPM_LEVELS
uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];
clock_table->NumDispClkLevelsEnabled <= VG_NUM_DPPCLK_DPM_LEVELS) {
bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, VG_NUM_DPPCLK_DPM_LEVELS);