drivers/gpu/drm/i915/gt/intel_engine_cs.c

198

{ .graphics_ver = 7, .base = VEBOX_RING_BASE }

drivers/gpu/drm/i915/gt/intel_engine_regs.h

44

#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

45

#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

46

#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))

drivers/gpu/drm/i915/gt/intel_rc6.c

466

(intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {

drivers/gpu/drm/i915/gvt/handlers.c

2191

MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \

drivers/gpu/drm/i915/gvt/handlers.c

2820

MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/mmio_context.c

147

{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1263

MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

56

MMIO_F(prefix(VEBOX_RING_BASE), s); \

drivers/gpu/drm/xe/xe_hw_engine.c

208

.mmio_base = VEBOX_RING_BASE,