VDPU_SWREG
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109));
#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111));
#define VDPU_REG_REFER_BASE(i) (VDPU_SWREG(84 + (i)))
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108));
reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
vdpu_write(vpu, reg, VDPU_SWREG(57));
#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63)
#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
#define VDPU_REG_REFER0_BASE VDPU_SWREG(131)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
#define VDPU_REG_REFER2_BASE VDPU_SWREG(134)
#define VDPU_REG_REFER3_BASE VDPU_SWREG(135)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
#define VDPU_REG_REFER1_BASE VDPU_SWREG(148)
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));
vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));
reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
vdpu_write(vpu, reg, VDPU_SWREG(57));