drivers/gpu/drm/i915/gt/intel_engine_cs.c

143

[VCS1] = {

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1704

[VCS1] = MSG_IDLE_VCS1,

drivers/gpu/drm/i915/gt/intel_engine_cs.c

413

[VCS1] = GEN11_GRDOM_MEDIA2,

drivers/gpu/drm/i915/gt/intel_engine_cs.c

438

[VCS1] = GEN8_GRDOM_MEDIA2,

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3502

[VCS1] = GEN8_VCS1_IRQ_SHIFT,

drivers/gpu/drm/i915/gt/intel_mocs.c

573

[VCS1] = __GEN9_VCS1_MOCS0,

drivers/gpu/drm/i915/gvt/cmd_parser.c

1174

[VCS1] = {

drivers/gpu/drm/i915/gvt/cmd_parser.c

434

#define R_VCS2 BIT(VCS1)

drivers/gpu/drm/i915/gvt/cmd_parser.c

648

[VCS1] = {

drivers/gpu/drm/i915/gvt/execlist.c

52

[VCS1] = VCS2_AS_CONTEXT_SWITCH,

drivers/gpu/drm/i915/gvt/handlers.c

2116

id = VCS1;

drivers/gpu/drm/i915/gvt/handlers.c

2192

if (HAS_ENGINE(gvt->gt, VCS1)) \

drivers/gpu/drm/i915/gvt/handlers.c

362

engine_mask |= BIT(VCS1);

drivers/gpu/drm/i915/gvt/interrupt.c

601

if (HAS_ENGINE(gvt->gt, VCS1)) {

drivers/gpu/drm/i915/gvt/mmio_context.c

145

{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */

drivers/gpu/drm/i915/gvt/mmio_context.c

173

[VCS1] = 0xca00,

drivers/gpu/drm/i915/gvt/mmio_context.c

360

[VCS1] = 0x4268,

drivers/gpu/drm/i915/gvt/mmio_context.c

417

[VCS1] = 0xca00,

drivers/gpu/drm/i915/i915_pci.c

447

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

drivers/gpu/drm/i915/i915_pci.c

498

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)

drivers/gpu/drm/i915/i915_pci.c

560

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

drivers/gpu/drm/i915/i915_pci.c

581

BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

57

if (HAS_ENGINE(to_gt(iter->i915), VCS1)) \