VCPU_REGS_RAX
int reg = VCPU_REGS_RAX;
while (reg >= VCPU_REGS_RAX) {
if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
eax = reg_read(ctxt, VCPU_REGS_RAX);
*reg_write(ctxt, VCPU_REGS_RAX) = eax;
flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
eax = reg_read(ctxt, VCPU_REGS_RAX);
u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
ghcb_set_rax(ghcb, vcpu->arch.regs[VCPU_REGS_RAX]);
vcpu->arch.regs[VCPU_REGS_RAX] = kvm_ghcb_get_rax_if_valid(svm);
if (vcpu->arch.regs[VCPU_REGS_RAX] == 0xd)
if (vcpu->arch.regs[VCPU_REGS_RAX] != sev->vmsa_features) {
vcpu->arch.regs[VCPU_REGS_RAX], sev->vmsa_features);
data_gpa = vcpu->arch.regs[VCPU_REGS_RAX];
vcpu->arch.regs[VCPU_REGS_RAX] = cpuid_fn;
cpuid_value = vcpu->arch.regs[VCPU_REGS_RAX];
save->rax = svm->vcpu.arch.regs[VCPU_REGS_RAX];
svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
BIT_ULL(VCPU_REGS_RAX) | \
int index = VCPU_REGS_RAX;
input = (u64)kvm_register_read(vcpu, VCPU_REGS_RAX);