VCPU_REGS_RCX
address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
rcx = reg_read(ctxt, VCPU_REGS_RCX);
*reg_write(ctxt, VCPU_REGS_RCX) = 0;
tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
register_address_increment(ctxt, VCPU_REGS_RCX, -1);
if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
ecx = reg_read(ctxt, VCPU_REGS_RCX);
*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
ecx = reg_read(ctxt, VCPU_REGS_RCX);
u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
register_address_increment(ctxt, VCPU_REGS_RCX, -count);
if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
ghcb_set_rcx(ghcb, vcpu->arch.regs[VCPU_REGS_RCX]);
vcpu->arch.regs[VCPU_REGS_RCX] = kvm_ghcb_get_rcx_if_valid(svm);
vcpu->arch.regs[VCPU_REGS_RCX] = 0;
cpuid_value = vcpu->arch.regs[VCPU_REGS_RCX];
save->rcx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
"rcx:", vcpu->arch.regs[VCPU_REGS_RCX],
BIT_ULL(VCPU_REGS_RCX) | \