VCO_REF_CLK_RATE
u64 fref = VCO_REF_CLK_RATE;
ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
u64 ref_clk = VCO_REF_CLK_RATE;
VCO_REF_CLK_RATE);
if (!dsi_pll_10nm_vco_recalc_rate(&pll_10nm->clk_hw, VCO_REF_CLK_RATE))
DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
period = (u32)VCO_REF_CLK_RATE / 1000;
ref = VCO_REF_CLK_RATE;
u64 fref = VCO_REF_CLK_RATE;
u64 fref = VCO_REF_CLK_RATE;
if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
rem = rate % VCO_REF_CLK_RATE;
div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
u32 ref_clk = VCO_REF_CLK_RATE;
ref_clk += (doubler * VCO_REF_CLK_RATE);
val = VCO_REF_CLK_RATE / 10;
u64 fref = VCO_REF_CLK_RATE;
ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
u64 ref_clk = VCO_REF_CLK_RATE;
VCO_REF_CLK_RATE);
if (!dsi_pll_7nm_vco_recalc_rate(&pll_7nm->clk_hw, VCO_REF_CLK_RATE))