VCLK0_FB_DIV
N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)];
tmp = VCLK0_FB_DIV + par->clk_wr_offset;
pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;