Symbol: VC5_CLK_OUTPUT_CFG0_PWR_SHIFT
drivers/clk/clk-versaclock5.c
107
#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
drivers/clk/clk-versaclock5.c
108
#define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
drivers/clk/clk-versaclock5.c
109
#define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
drivers/clk/clk-versaclock5.c
110
#define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)