drivers/gpu/drm/vc4/vc4_crtc.c

302

ret |= VC4_SET_FIELD((level >> 6),

drivers/gpu/drm/vc4/vc4_crtc.c

305

return ret | VC4_SET_FIELD(level & 0x3f,

drivers/gpu/drm/vc4/vc4_crtc.c

386

VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,

drivers/gpu/drm/vc4/vc4_crtc.c

388

VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,

drivers/gpu/drm/vc4/vc4_crtc.c

392

VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,

drivers/gpu/drm/vc4/vc4_crtc.c

394

VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,

drivers/gpu/drm/vc4/vc4_crtc.c

418

VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |

drivers/gpu/drm/vc4/vc4_crtc.c

419

VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));

drivers/gpu/drm/vc4/vc4_crtc.c

421

VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |

drivers/gpu/drm/vc4/vc4_crtc.c

422

VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));

drivers/gpu/drm/vc4/vc4_crtc.c

434

: VC4_SET_FIELD(field_delay,

drivers/gpu/drm/vc4/vc4_crtc.c

447

VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |

drivers/gpu/drm/vc4/vc4_crtc.c

448

VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));

drivers/gpu/drm/vc4/vc4_crtc.c

450

VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |

drivers/gpu/drm/vc4/vc4_crtc.c

451

VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));

drivers/gpu/drm/vc4/vc4_crtc.c

458

VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,

drivers/gpu/drm/vc4/vc4_crtc.c

463

VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_WIDTH) |

drivers/gpu/drm/vc4/vc4_crtc.c

464

VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_IDLE) |

drivers/gpu/drm/vc4/vc4_crtc.c

469

VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |

drivers/gpu/drm/vc4/vc4_crtc.c

470

VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |

drivers/gpu/drm/vc4/vc4_crtc.c

474

VC4_SET_FIELD(vc4_encoder->clock_select,

drivers/gpu/drm/vc4/vc4_dpi.c

161

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT);

drivers/gpu/drm/vc4/vc4_dpi.c

171

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,

drivers/gpu/drm/vc4/vc4_dpi.c

175

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,

drivers/gpu/drm/vc4/vc4_dpi.c

177

dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR,

drivers/gpu/drm/vc4/vc4_dpi.c

181

dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);

drivers/gpu/drm/vc4/vc4_dpi.c

184

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,

drivers/gpu/drm/vc4/vc4_dpi.c

188

dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);

drivers/gpu/drm/vc4/vc4_dpi.c

191

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,

drivers/gpu/drm/vc4/vc4_dpi.c

195

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1,

drivers/gpu/drm/vc4/vc4_dpi.c

199

dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2,

drivers/gpu/drm/vc4/vc4_dsi.c

1027

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1029

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),

drivers/gpu/drm/vc4/vc4_dsi.c

1031

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1035

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1037

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),

drivers/gpu/drm/vc4/vc4_dsi.c

1041

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1045

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1047

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),

drivers/gpu/drm/vc4/vc4_dsi.c

1049

VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),

drivers/gpu/drm/vc4/vc4_dsi.c

1053

VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),

drivers/gpu/drm/vc4/vc4_dsi.c

1055

VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),

drivers/gpu/drm/vc4/vc4_dsi.c

1058

VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));

drivers/gpu/drm/vc4/vc4_dsi.c

1069

DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,

drivers/gpu/drm/vc4/vc4_dsi.c

1074

VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |

drivers/gpu/drm/vc4/vc4_dsi.c

1075

VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |

drivers/gpu/drm/vc4/vc4_dsi.c

1076

VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |

drivers/gpu/drm/vc4/vc4_dsi.c

1077

VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));

drivers/gpu/drm/vc4/vc4_dsi.c

1080

VC4_SET_FIELD(dsi_esc_timing(1000000),

drivers/gpu/drm/vc4/vc4_dsi.c

1092

VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :

drivers/gpu/drm/vc4/vc4_dsi.c

1093

VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));

drivers/gpu/drm/vc4/vc4_dsi.c

1112

VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,

drivers/gpu/drm/vc4/vc4_dsi.c

1131

VC4_SET_FIELD(dsi->divider,

drivers/gpu/drm/vc4/vc4_dsi.c

1133

VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |

drivers/gpu/drm/vc4/vc4_dsi.c

1134

VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,

drivers/gpu/drm/vc4/vc4_dsi.c

1185

pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);

drivers/gpu/drm/vc4/vc4_dsi.c

1186

pkth |= VC4_SET_FIELD(packet.header[1] |

drivers/gpu/drm/vc4/vc4_dsi.c

1211

pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);

drivers/gpu/drm/vc4/vc4_dsi.c

1215

pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,

drivers/gpu/drm/vc4/vc4_dsi.c

1218

pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,

drivers/gpu/drm/vc4/vc4_dsi.c

1242

pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);

drivers/gpu/drm/vc4/vc4_dsi.c

1246

pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,

drivers/gpu/drm/vc4/vc4_dsi.c

1249

pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,

drivers/gpu/drm/vc4/vc4_dsi.c

1265

VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,

drivers/gpu/drm/vc4/vc4_dsi.c

942

u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |

drivers/gpu/drm/vc4/vc4_dsi.c

943

VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));

drivers/gpu/drm/vc4/vc4_dsi.c

957

VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |

drivers/gpu/drm/vc4/vc4_dsi.c

958

VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |

drivers/gpu/drm/vc4/vc4_dsi.c

959

VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));

drivers/gpu/drm/vc4/vc4_dsi.c

961

u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |

drivers/gpu/drm/vc4/vc4_dsi.c

962

VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |

drivers/gpu/drm/vc4/vc4_dsi.c

963

VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |

drivers/gpu/drm/vc4/vc4_dsi.c

964

VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |

drivers/gpu/drm/vc4/vc4_dsi.c

965

VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |

drivers/gpu/drm/vc4/vc4_dsi.c

966

VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |

drivers/gpu/drm/vc4/vc4_dsi.c

967

VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));

drivers/gpu/drm/vc4/vc4_gem.c

449

VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |

drivers/gpu/drm/vc4/vc4_gem.c

450

VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |

drivers/gpu/drm/vc4/vc4_gem.c

451

VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |

drivers/gpu/drm/vc4/vc4_gem.c

452

VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));

drivers/gpu/drm/vc4/vc4_gem.c

464

VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |

drivers/gpu/drm/vc4/vc4_gem.c

465

VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC));

drivers/gpu/drm/vc4/vc4_hdmi.c

1207

u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,

drivers/gpu/drm/vc4/vc4_hdmi.c

1226

csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,

drivers/gpu/drm/vc4/vc4_hdmi.c

1231

csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,

drivers/gpu/drm/vc4/vc4_hdmi.c

1234

if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,

drivers/gpu/drm/vc4/vc4_hdmi.c

1269

u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,

drivers/gpu/drm/vc4/vc4_hdmi.c

1271

VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,

drivers/gpu/drm/vc4/vc4_hdmi.c

1273

VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));

drivers/gpu/drm/vc4/vc4_hdmi.c

1274

u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |

drivers/gpu/drm/vc4/vc4_hdmi.c

1275

VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +

drivers/gpu/drm/vc4/vc4_hdmi.c

1278

u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |

drivers/gpu/drm/vc4/vc4_hdmi.c

1279

VC4_SET_FIELD(mode->crtc_vtotal -

drivers/gpu/drm/vc4/vc4_hdmi.c

1294

VC4_SET_FIELD(mode->hdisplay * pixel_rep,

drivers/gpu/drm/vc4/vc4_hdmi.c

1298

VC4_SET_FIELD((mode->htotal -

drivers/gpu/drm/vc4/vc4_hdmi.c

1301

VC4_SET_FIELD((mode->hsync_end -

drivers/gpu/drm/vc4/vc4_hdmi.c

1304

VC4_SET_FIELD((mode->hsync_start -

drivers/gpu/drm/vc4/vc4_hdmi.c

1316

reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);

drivers/gpu/drm/vc4/vc4_hdmi.c

1333

u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,

drivers/gpu/drm/vc4/vc4_hdmi.c

1335

VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,

drivers/gpu/drm/vc4/vc4_hdmi.c

1337

VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));

drivers/gpu/drm/vc4/vc4_hdmi.c

1338

u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),

drivers/gpu/drm/vc4/vc4_hdmi.c

1340

VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +

drivers/gpu/drm/vc4/vc4_hdmi.c

1343

u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |

drivers/gpu/drm/vc4/vc4_hdmi.c

1344

VC4_SET_FIELD(mode->crtc_vtotal -

drivers/gpu/drm/vc4/vc4_hdmi.c

1360

VC4_SET_FIELD(mode->hdisplay * pixel_rep,

drivers/gpu/drm/vc4/vc4_hdmi.c

1362

VC4_SET_FIELD((mode->hsync_start -

drivers/gpu/drm/vc4/vc4_hdmi.c

1367

VC4_SET_FIELD((mode->htotal -

drivers/gpu/drm/vc4/vc4_hdmi.c

1370

VC4_SET_FIELD((mode->hsync_end -

drivers/gpu/drm/vc4/vc4_hdmi.c

1404

reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |

drivers/gpu/drm/vc4/vc4_hdmi.c

1405

VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);

drivers/gpu/drm/vc4/vc4_hdmi.c

1410

reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);

drivers/gpu/drm/vc4/vc4_hdmi.c

1421

reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);

drivers/gpu/drm/vc4/vc4_hdmi.c

1918

VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |

drivers/gpu/drm/vc4/vc4_hdmi.c

1919

VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));

drivers/gpu/drm/vc4/vc4_hdmi.c

1941

VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));

drivers/gpu/drm/vc4/vc4_hdmi.c

2147

VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2159

VC4_SET_FIELD(mai_sample_rate,

drivers/gpu/drm/vc4/vc4_hdmi.c

2161

VC4_SET_FIELD(mai_audio_format,

drivers/gpu/drm/vc4/vc4_hdmi.c

2168

VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);

drivers/gpu/drm/vc4/vc4_hdmi.c

2171

audio_packet_config |= VC4_SET_FIELD(channel_mask,

drivers/gpu/drm/vc4/vc4_hdmi.c

2178

VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2179

VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2180

VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2181

VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW));

drivers/gpu/drm/vc4/vc4_hdmi.c

2186

VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2187

VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2188

VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2189

VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));

drivers/gpu/drm/vc4/vc4_hdmi.c

2193

VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2194

VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2195

VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |

drivers/gpu/drm/vc4/vc4_hdmi.c

2196

VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));

drivers/gpu/drm/vc4/vc4_hdmi.c

2206

VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));

drivers/gpu/drm/vc4/vc4_hdmi.c

975

csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,

drivers/gpu/drm/vc4/vc4_hdmi.c

991

csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1002

VC4_SET_FIELD(2, VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1003

VC4_SET_FIELD(1, VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1009

VC4_SET_FIELD(chan0_settings->ext_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1011

VC4_SET_FIELD(chan0_settings->ffe_enable,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1013

VC4_SET_FIELD(chan0_settings->slew_rate_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1015

VC4_SET_FIELD(chan0_settings->ffe_post_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1017

VC4_SET_FIELD(chan0_settings->ldmos_bias_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1019

VC4_SET_FIELD(chan0_settings->com_mode_ldmos_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1021

VC4_SET_FIELD(chan0_settings->edge_sel,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1023

VC4_SET_FIELD(chan0_settings->ext_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1025

VC4_SET_FIELD(chan0_settings->term_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1027

VC4_SET_FIELD(chan0_settings->ext_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1029

VC4_SET_FIELD(chan0_settings->int_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1031

VC4_SET_FIELD(chan0_settings->int_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1033

VC4_SET_FIELD(chan0_settings->int_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1035

VC4_SET_FIELD(chan0_settings->main_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1037

VC4_SET_FIELD(chan0_settings->post_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1039

VC4_SET_FIELD(chan0_settings->slew_ctl_slow_loading,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1041

VC4_SET_FIELD(chan0_settings->slew_ctl_slow_driving,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1043

VC4_SET_FIELD(chan0_settings->ffe_pre_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1050

VC4_SET_FIELD(chan1_settings->ext_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1052

VC4_SET_FIELD(chan1_settings->ffe_enable,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1054

VC4_SET_FIELD(chan1_settings->slew_rate_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1056

VC4_SET_FIELD(chan1_settings->ffe_post_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1058

VC4_SET_FIELD(chan1_settings->ldmos_bias_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1060

VC4_SET_FIELD(chan1_settings->com_mode_ldmos_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1062

VC4_SET_FIELD(chan1_settings->edge_sel,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1064

VC4_SET_FIELD(chan1_settings->ext_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1066

VC4_SET_FIELD(chan1_settings->term_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1068

VC4_SET_FIELD(chan1_settings->ext_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1070

VC4_SET_FIELD(chan1_settings->int_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1072

VC4_SET_FIELD(chan1_settings->int_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1074

VC4_SET_FIELD(chan1_settings->int_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1076

VC4_SET_FIELD(chan1_settings->main_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1078

VC4_SET_FIELD(chan1_settings->post_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1080

VC4_SET_FIELD(chan1_settings->slew_ctl_slow_loading,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1082

VC4_SET_FIELD(chan1_settings->slew_ctl_slow_driving,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1084

VC4_SET_FIELD(chan1_settings->ffe_pre_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1091

VC4_SET_FIELD(chan2_settings->ext_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1093

VC4_SET_FIELD(chan2_settings->ffe_enable,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1095

VC4_SET_FIELD(chan2_settings->slew_rate_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1097

VC4_SET_FIELD(chan2_settings->ffe_post_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1099

VC4_SET_FIELD(chan2_settings->ldmos_bias_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1101

VC4_SET_FIELD(chan2_settings->com_mode_ldmos_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1103

VC4_SET_FIELD(chan2_settings->edge_sel,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1105

VC4_SET_FIELD(chan2_settings->ext_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1107

VC4_SET_FIELD(chan2_settings->term_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1109

VC4_SET_FIELD(chan2_settings->ext_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1111

VC4_SET_FIELD(chan2_settings->int_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1113

VC4_SET_FIELD(chan2_settings->int_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1115

VC4_SET_FIELD(chan2_settings->int_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1117

VC4_SET_FIELD(chan2_settings->main_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1119

VC4_SET_FIELD(chan2_settings->post_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1121

VC4_SET_FIELD(chan2_settings->slew_ctl_slow_loading,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1123

VC4_SET_FIELD(chan2_settings->slew_ctl_slow_driving,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1125

VC4_SET_FIELD(chan2_settings->ffe_pre_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1132

VC4_SET_FIELD(clock_settings->ext_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1134

VC4_SET_FIELD(clock_settings->ffe_enable,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1136

VC4_SET_FIELD(clock_settings->slew_rate_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1138

VC4_SET_FIELD(clock_settings->ffe_post_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1140

VC4_SET_FIELD(clock_settings->ldmos_bias_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1142

VC4_SET_FIELD(clock_settings->com_mode_ldmos_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1144

VC4_SET_FIELD(clock_settings->edge_sel,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1146

VC4_SET_FIELD(clock_settings->ext_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1148

VC4_SET_FIELD(clock_settings->term_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1150

VC4_SET_FIELD(clock_settings->ext_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1152

VC4_SET_FIELD(clock_settings->int_current_src_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1154

VC4_SET_FIELD(clock_settings->int_current_ctl,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1156

VC4_SET_FIELD(clock_settings->int_current_src_hs_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1158

VC4_SET_FIELD(clock_settings->main_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1160

VC4_SET_FIELD(clock_settings->post_tap_current_select,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1162

VC4_SET_FIELD(clock_settings->slew_ctl_slow_loading,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1164

VC4_SET_FIELD(clock_settings->slew_ctl_slow_driving,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

1166

VC4_SET_FIELD(clock_settings->ffe_pre_tap_en,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

441

VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

446

VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

449

VC4_SET_FIELD(phy_get_rm_offset(vco_freq),

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

454

VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

457

VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

458

VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

464

VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

469

VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

470

VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

471

VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

475

VC4_SET_FIELD(2, VC4_HDMI_RM_FORMAT_SHIFT));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

479

VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

488

VC4_SET_FIELD(phy_get_cp_current(vco_freq),

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

490

VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

491

VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP1) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

492

VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

493

VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) |

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

494

VC4_SET_FIELD(6, VC4_HDMI_TX_PHY_CTL_3_RZ));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

510

VC4_SET_FIELD(chan0_settings->amplitude.preemphasis,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

512

VC4_SET_FIELD(chan0_settings->amplitude.main_driver,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

514

VC4_SET_FIELD(chan1_settings->amplitude.preemphasis,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

516

VC4_SET_FIELD(chan1_settings->amplitude.main_driver,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

518

VC4_SET_FIELD(chan2_settings->amplitude.preemphasis,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

520

VC4_SET_FIELD(chan2_settings->amplitude.main_driver,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

522

VC4_SET_FIELD(clock_settings->amplitude.preemphasis,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

524

VC4_SET_FIELD(clock_settings->amplitude.main_driver,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

529

VC4_SET_FIELD(chan0_settings->res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

531

VC4_SET_FIELD(chan1_settings->res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

533

VC4_SET_FIELD(chan2_settings->res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

535

VC4_SET_FIELD(clock_settings->res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

539

VC4_SET_FIELD(chan0_settings->term_res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

541

VC4_SET_FIELD(chan1_settings->term_res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

543

VC4_SET_FIELD(chan2_settings->term_res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

545

VC4_SET_FIELD(clock_settings->term_res_sel_data,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

547

VC4_SET_FIELD(phy_get_vco_gain(vco_freq),

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

551

VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_0],

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

553

VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_1],

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

555

VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_2],

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

557

VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_CK],

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

984

VC4_SET_FIELD(54, VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ));

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

990

VC4_SET_FIELD(phy_get_rm_offset(vco_freq),

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

995

VC4_SET_FIELD(vco_div,

drivers/gpu/drm/vc4/vc4_hdmi_phy.c

999

VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));

drivers/gpu/drm/vc4/vc4_hvs.c

1316

reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));

drivers/gpu/drm/vc4/vc4_hvs.c

1321

reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));

drivers/gpu/drm/vc4/vc4_hvs.c

1326

reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));

drivers/gpu/drm/vc4/vc4_hvs.c

1331

reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));

drivers/gpu/drm/vc4/vc4_hvs.c

1374

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);

drivers/gpu/drm/vc4/vc4_hvs.c

1375

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);

drivers/gpu/drm/vc4/vc4_hvs.c

1376

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);

drivers/gpu/drm/vc4/vc4_hvs.c

1385

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0);

drivers/gpu/drm/vc4/vc4_hvs.c

1386

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1);

drivers/gpu/drm/vc4/vc4_hvs.c

1387

dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2);

drivers/gpu/drm/vc4/vc4_hvs.c

1485

VC4_SET_FIELD(8, SCALER6_CONTROL_PF_LINES) |

drivers/gpu/drm/vc4/vc4_hvs.c

1486

VC4_SET_FIELD(15, SCALER6_CONTROL_MAX_REQS));

drivers/gpu/drm/vc4/vc4_hvs.c

1606

VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |

drivers/gpu/drm/vc4/vc4_hvs.c

1607

VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE));

drivers/gpu/drm/vc4/vc4_hvs.c

1613

VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |

drivers/gpu/drm/vc4/vc4_hvs.c

1614

VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE));

drivers/gpu/drm/vc4/vc4_hvs.c

1620

VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |

drivers/gpu/drm/vc4/vc4_hvs.c

1621

VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE));

drivers/gpu/drm/vc4/vc4_hvs.c

650

dispctrl |= VC4_SET_FIELD(mode->hdisplay,

drivers/gpu/drm/vc4/vc4_hvs.c

652

VC4_SET_FIELD(mode->vdisplay,

drivers/gpu/drm/vc4/vc4_hvs.c

657

dispctrl |= VC4_SET_FIELD(mode->hdisplay,

drivers/gpu/drm/vc4/vc4_hvs.c

659

VC4_SET_FIELD(mode->vdisplay,

drivers/gpu/drm/vc4/vc4_hvs.c

709

VC4_SET_FIELD(mode->hdisplay - 1,

drivers/gpu/drm/vc4/vc4_hvs.c

712

VC4_SET_FIELD(mode->vdisplay - 1,

drivers/gpu/drm/vc4/vc4_hvs.c

848

VC4_SET_FIELD(vc4_state->mm.start,

drivers/gpu/drm/vc4/vc4_kms.c

146

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),

drivers/gpu/drm/vc4/vc4_kms.c

148

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),

drivers/gpu/drm/vc4/vc4_kms.c

150

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),

drivers/gpu/drm/vc4/vc4_kms.c

153

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),

drivers/gpu/drm/vc4/vc4_kms.c

155

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),

drivers/gpu/drm/vc4/vc4_kms.c

157

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),

drivers/gpu/drm/vc4/vc4_kms.c

160

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),

drivers/gpu/drm/vc4/vc4_kms.c

162

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),

drivers/gpu/drm/vc4/vc4_kms.c

164

VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),

drivers/gpu/drm/vc4/vc4_kms.c

169

VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));

drivers/gpu/drm/vc4/vc4_kms.c

244

dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);

drivers/gpu/drm/vc4/vc4_kms.c

246

dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);

drivers/gpu/drm/vc4/vc4_kms.c

284

VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));

drivers/gpu/drm/vc4/vc4_kms.c

296

VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));

drivers/gpu/drm/vc4/vc4_kms.c

308

VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));

drivers/gpu/drm/vc4/vc4_kms.c

321

VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));

drivers/gpu/drm/vc4/vc4_kms.c

374

VC4_SET_FIELD(mux, SCALER6_CONTROL_DSP1_TARGET));

drivers/gpu/drm/vc4/vc4_plane.c

1046

VC4_SET_FIELD(refcount->upm.start / HVS_UBM_WORD_SIZE,

drivers/gpu/drm/vc4/vc4_plane.c

1048

VC4_SET_FIELD(vc4_state->upm_handle[i] - 1,

drivers/gpu/drm/vc4/vc4_plane.c

1050

VC4_SET_FIELD(vc4_state->upm_buffer_lines,

drivers/gpu/drm/vc4/vc4_plane.c

1133

return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,

drivers/gpu/drm/vc4/vc4_plane.c

1138

return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,

drivers/gpu/drm/vc4/vc4_plane.c

1142

return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,

drivers/gpu/drm/vc4/vc4_plane.c

1146

return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,

drivers/gpu/drm/vc4/vc4_plane.c

1164

return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,

drivers/gpu/drm/vc4/vc4_plane.c

1169

return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,

drivers/gpu/drm/vc4/vc4_plane.c

1173

return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE,

drivers/gpu/drm/vc4/vc4_plane.c

1177

return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE,

drivers/gpu/drm/vc4/vc4_plane.c

1197

return VC4_SET_FIELD(SCALER6D_CTL0_ALPHA_MASK_FIXED,

drivers/gpu/drm/vc4/vc4_plane.c

1200

return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK);

drivers/gpu/drm/vc4/vc4_plane.c

1274

pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);

drivers/gpu/drm/vc4/vc4_plane.c

1332

pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |

drivers/gpu/drm/vc4/vc4_plane.c

1333

VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |

drivers/gpu/drm/vc4/vc4_plane.c

1334

VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |

drivers/gpu/drm/vc4/vc4_plane.c

1335

VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));

drivers/gpu/drm/vc4/vc4_plane.c

1441

pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);

drivers/gpu/drm/vc4/vc4_plane.c

1488

VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |

drivers/gpu/drm/vc4/vc4_plane.c

1491

VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |

drivers/gpu/drm/vc4/vc4_plane.c

1493

VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |

drivers/gpu/drm/vc4/vc4_plane.c

1494

VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));

drivers/gpu/drm/vc4/vc4_plane.c

1499

VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |

drivers/gpu/drm/vc4/vc4_plane.c

1500

VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |

drivers/gpu/drm/vc4/vc4_plane.c

1501

VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));

drivers/gpu/drm/vc4/vc4_plane.c

1506

VC4_SET_FIELD(vc4_state->crtc_w,

drivers/gpu/drm/vc4/vc4_plane.c

1508

VC4_SET_FIELD(vc4_state->crtc_h,

drivers/gpu/drm/vc4/vc4_plane.c

1517

VC4_SET_FIELD(width, SCALER_POS2_WIDTH) |

drivers/gpu/drm/vc4/vc4_plane.c

1518

VC4_SET_FIELD(height, SCALER_POS2_HEIGHT));

drivers/gpu/drm/vc4/vc4_plane.c

1529

VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |

drivers/gpu/drm/vc4/vc4_plane.c

1532

VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |

drivers/gpu/drm/vc4/vc4_plane.c

1533

VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |

drivers/gpu/drm/vc4/vc4_plane.c

1542

VC4_SET_FIELD(vc4_state->crtc_x,

drivers/gpu/drm/vc4/vc4_plane.c

1546

VC4_SET_FIELD(vc4_state->crtc_y,

drivers/gpu/drm/vc4/vc4_plane.c

1552

VC4_SET_FIELD(state->alpha >> 4,

drivers/gpu/drm/vc4/vc4_plane.c

1562

VC4_SET_FIELD(vc4_state->crtc_w,

drivers/gpu/drm/vc4/vc4_plane.c

1564

VC4_SET_FIELD(vc4_state->crtc_h,

drivers/gpu/drm/vc4/vc4_plane.c

1571

VC4_SET_FIELD(width, SCALER5_POS2_WIDTH) |

drivers/gpu/drm/vc4/vc4_plane.c

1572

VC4_SET_FIELD(height, SCALER5_POS2_HEIGHT));

drivers/gpu/drm/vc4/vc4_plane.c

1603

VC4_SET_FIELD(fb->pitches[i],

drivers/gpu/drm/vc4/vc4_plane.c

1659

u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,

drivers/gpu/drm/vc4/vc4_plane.c

1674

VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);

drivers/gpu/drm/vc4/vc4_plane.c

1724

ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),

drivers/gpu/drm/vc4/vc4_plane.c

1728

ret |= VC4_SET_FIELD(color_encoding + (color_range * 3),

drivers/gpu/drm/vc4/vc4_plane.c

1906

pitch0 = VC4_SET_FIELD(param, SCALER6_PTR2_PITCH) |

drivers/gpu/drm/vc4/vc4_plane.c

1907

VC4_SET_FIELD(fetch_count - 1, SCALER6_PTR2_FETCH_COUNT);

drivers/gpu/drm/vc4/vc4_plane.c

1951

VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) |

drivers/gpu/drm/vc4/vc4_plane.c

1954

VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) |

drivers/gpu/drm/vc4/vc4_plane.c

1955

VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) |

drivers/gpu/drm/vc4/vc4_plane.c

1956

VC4_SET_FIELD(scl0, SCALER6_CTL0_SCL0_MODE) |

drivers/gpu/drm/vc4/vc4_plane.c

1957

VC4_SET_FIELD(hvs_format, SCALER6_CTL0_PIXEL_FORMAT));

drivers/gpu/drm/vc4/vc4_plane.c

1962

VC4_SET_FIELD(vc4_state->crtc_y, SCALER6_POS0_START_Y) |

drivers/gpu/drm/vc4/vc4_plane.c

1964

VC4_SET_FIELD(vc4_state->crtc_x, SCALER6_POS0_START_X));

drivers/gpu/drm/vc4/vc4_plane.c

1971

VC4_SET_FIELD(state->alpha >> 4, SCALER5_CTL2_ALPHA));

drivers/gpu/drm/vc4/vc4_plane.c

1976

VC4_SET_FIELD(vc4_state->crtc_h - 1,

drivers/gpu/drm/vc4/vc4_plane.c

1978

VC4_SET_FIELD(vc4_state->crtc_w - 1,

drivers/gpu/drm/vc4/vc4_plane.c

1984

VC4_SET_FIELD(height - 1,

drivers/gpu/drm/vc4/vc4_plane.c

1986

VC4_SET_FIELD(width - 1,

drivers/gpu/drm/vc4/vc4_plane.c

2007

VC4_SET_FIELD(upper_32_bits(paddr) & 0xff,

drivers/gpu/drm/vc4/vc4_plane.c

2017

VC4_SET_FIELD(fb->pitches[i],

drivers/gpu/drm/vc4/vc4_plane.c

2072

VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,

drivers/gpu/drm/vc4/vc4_plane.c

2089

VC4_SET_FIELD(vc4_state->dlist_count, SCALER6_CTL0_NEXT);

drivers/gpu/drm/vc4/vc4_plane.c

2235

value |= VC4_SET_FIELD(upper_32_bits(dma_addr) & 0xff,

drivers/gpu/drm/vc4/vc4_plane.c

590

VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |

drivers/gpu/drm/vc4/vc4_plane.c

591

VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));

drivers/gpu/drm/vc4/vc4_plane.c

593

VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));

drivers/gpu/drm/vc4/vc4_plane.c

652

VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |

drivers/gpu/drm/vc4/vc4_plane.c

658

VC4_SET_FIELD(phase, SCALER_PPF_IPHASE));

drivers/gpu/drm/vc4/vc4_render_cl.c

86

VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,

drivers/gpu/drm/vc4/vc4_txp.c

320

VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);

drivers/gpu/drm/vc4/vc4_txp.c

323

ctrl |= VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE);

drivers/gpu/drm/vc4/vc4_txp.c

355

VC4_SET_FIELD(hdisplay, TXP_WIDTH) |

drivers/gpu/drm/vc4/vc4_txp.c

356

VC4_SET_FIELD(vdisplay, TXP_HEIGHT));

drivers/gpu/drm/vc4/vc4_validate.c

416

VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32,

drivers/gpu/drm/vc4/vc4_validate.c

418

VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128,