V4L2_DV_BT_STD_CVT
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
if (bt->standards == 0 || (bt->standards & V4L2_DV_BT_STD_CVT)) {
V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
if ((bt->standards & (V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF)) &&
(bt->standards & V4L2_DV_BT_STD_CVT) ? " CVT" : "",
t.bt.standards = V4L2_DV_BT_STD_CVT;
if ((bt->standards & V4L2_DV_BT_STD_CVT) && (bt->vsync == 8))
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \