UVD_POWER_STATUS__UVD_PG_MODE_MASK
WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;