UVD_HWIP
[UVD_HWIP] = "UVD/JPEG/VCN",
[UVD_HWIP] = UVD_HWID,
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
amdgpu_ip_version(adev, UVD_HWIP, 0));
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
amdgpu_ip_version(adev, UVD_HWIP, 0));
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);
if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
VCN_HWIP = UVD_HWIP,
IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
} else if (block_type == UVD_HWIP) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
case UVD_HWIP:
offset = adev->reg_offset[UVD_HWIP][ring->me][1];
amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) &&
(amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) {
if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) ||
amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1))
if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) {
amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);
if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) {
} else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {
adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
amdgpu_ip_version(adev, UVD_HWIP, 0));
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
reg -= p->adev->reg_offset[UVD_HWIP][0][1];
reg += p->adev->reg_offset[UVD_HWIP][1][1];
if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0))
if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));