UART_LSR_BI
port->read_status_mask |= UART_LSR_BI;
port->ignore_status_mask |= UART_LSR_BI;
if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
if (*status & UART_LSR_BI) {
if (*status & UART_LSR_BI)
status |= UART_LSR_BI;
if (status & (UART_LSR_BI | UART_LSR_PE |
if (status & UART_LSR_BI) {
if (status & (UART_LSR_BI)) {
info->read_status_mask |= UART_LSR_BI;
info->ignore_status_mask |= UART_LSR_BI;
if (status & UART_LSR_BI) {
info->read_status_mask |= UART_LSR_BI;
info->ignore_status_mask |= UART_LSR_BI;
info->read_status_mask |= UART_LSR_BI;
if (lsr & (UART_LSR_DR | UART_LSR_BI)) {
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
if (!(status & (UART_LSR_DR | UART_LSR_BI)))
if (status & (UART_LSR_DR | UART_LSR_BI)) {
(up->lsr_saved_flags & UART_LSR_BI))) {
up->lsr_saved_flags &= ~UART_LSR_BI;
if ((lsr & (UART_LSR_DR | UART_LSR_BI)) &&
up->lsr_saved_flags |= orig_lsr & UART_LSR_BI;
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
if (status & (UART_LSR_FE | UART_LSR_PE | UART_LSR_BI))
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
port->read_status_mask |= UART_LSR_BI;
port->ignore_status_mask |= UART_LSR_BI;
if (lsr & UART_LSR_BI) {
if (lsr & UART_LSR_BI) {
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
port->read_status_mask |= UART_LSR_BI;
port->ignore_status_mask |= UART_LSR_BI;
error_mask |= UART_LSR_BI;
ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
if (ch->ch_equeue[head] & UART_LSR_BI)
error_mask |= UART_LSR_BI;
if (linestatus & UART_LSR_BI) {
if (error & UART_LSR_BI)
if (status & UART_LSR_BI)
up->lsr_break_flag = UART_LSR_BI;
if (lsr & UART_LSR_BI) {
up->port.read_status_mask |= UART_LSR_BI;
up->port.ignore_status_mask |= UART_LSR_BI;
i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
if (lsr & UART_LSR_BI) {
if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
if (*status & UART_LSR_BI) {
if (*status & UART_LSR_BI) {
up->port.read_status_mask |= UART_LSR_BI;
up->port.ignore_status_mask |= UART_LSR_BI;
if (status & UART_LSR_BI)
up->lsr_break_flag = UART_LSR_BI;
tup->uport.ignore_status_mask |= UART_LSR_BI;
#define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
} else if (lsr & UART_LSR_BI) {
if (tup->uport.ignore_status_mask & UART_LSR_BI)
if (status & UART_LSR_BI)
up->lsr_break_flag = UART_LSR_BI;
if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
if (*status & UART_LSR_BI) {
if (*status & UART_LSR_BI) {
if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
up->port.read_status_mask |= UART_LSR_BI;
up->port.ignore_status_mask |= UART_LSR_BI;
if (lsr & UART_LSR_BI)
if (lsr & UART_LSR_BI)
if (lsr & UART_LSR_BI) {
if (lsr & UART_LSR_BI) {
if ((lsr & UART_LSR_BI) == UART_LSR_BI)
if (lsr_event & UART_LSR_BI) {
if (newLSR & UART_LSR_BI)
newLSR &= (u8) (UART_LSR_OE | UART_LSR_BI);
if (newLSR & UART_LSR_BI)
if (lsr & UART_LSR_BI) {
#define UART_LSR_BRK_ERROR_BITS (UART_LSR_BI|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)