UART_LSR_THRE
while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
bits = UART_LSR_TEMT | UART_LSR_THRE;
while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0);
if (lsr & (UART_LSR_THRE | UART_LSR_TEMT)) {
while (!(sinp(UART_LSR) & UART_LSR_THRE))
port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (lsr & UART_LSR_THRE)
if (iir == 0x02 && (status & UART_LSR_THRE))
if (status & UART_LSR_THRE)
info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (lsr & UART_LSR_THRE)
if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
(lsr & UART_LSR_THRE)) {
if (!(lsr & UART_LSR_THRE))
if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
if (status & UART_LSR_THRE && up->dma->tx_err) {
if (!(lsr & UART_LSR_THRE))
if (lsr & UART_LSR_THRE)
!(serial_in(up, UART_LSR) & UART_LSR_THRE))
if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
wait_for_xmitr(up, UART_LSR_THRE);
if (wait_for_lsr(up, UART_LSR_THRE))
wait_for_xmitr(up, UART_LSR_THRE);
if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
if (ch->ch_cached_lsr & UART_LSR_THRE) {
ch->ch_cached_lsr &= ~(UART_LSR_THRE);
if (linestatus & UART_LSR_THRE) {
while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
(UART_LSR_THRE | UART_LSR_DR))) {
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
wait_for_xmitr(priv, UART_LSR_THRE);
wait_for_xmitr(priv, UART_LSR_THRE);
if (lsr & UART_LSR_THRE)
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
if (status & UART_LSR_THRE)
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
} while (!(lsr & UART_LSR_THRE));
if ((data & (UART_LSR_TEMT | UART_LSR_THRE))
== (UART_LSR_TEMT | UART_LSR_THRE)) {
#define UART_LSR_BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
if (status & UART_LSR_THRE)
if ((inb(uart->base + UART_LSR) & UART_LSR_THRE) != 0) {