UART_DLM
udbg_uart_out(UART_DLM, dll >> 8);
dlm = udbg_uart_in(UART_DLM);
out_8(avr_addr + UART_DLM, quot >> 8); /* MS of divisor */
outb(quot >> 8, ser->port + UART_DLM); /* MS of divisor */
soutp(UART_DLM, 0);
sdio_out(port, UART_DLM, quot >> 8);
outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff);
early_out(port, UART_DLM, 0);
early_out(port, UART_DLM, (divisor >> 8) & 0xff);
unsigned char dlm = serial_in(up, UART_DLM);
serial_out(up, UART_DLM, value >> 8 & 0xff);
dlm = serial_port_in(port, UART_DLM);
serial_out(up, UART_DLM, value >> 8 & 0xff);
serial_out(up, UART_DLM, up->dlh);
serial_out(up, UART_DLM, 0);
serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
"DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
ark3116_write_reg(serial, UART_DLM, (priv->quot>>8) & 0xff);
ark3116_write_reg(serial, UART_DLM, (quot>>8) & 0xff);
uart->old_divisor_msb = inb(uart->base + UART_DLM);
,uart->base + UART_DLM); /* Divisor Latch High */
,uart->base + UART_DLM); /* Divisor Latch High */