arch/powerpc/kvm/emulate_loadstore.c

113

if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))

arch/powerpc/kvm/emulate_loadstore.c

133

if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))

arch/powerpc/kvm/emulate_loadstore.c

232

if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))

arch/powerpc/kvm/emulate_loadstore.c

256

if ((op.type & UPDATE) && (emulated != EMULATE_FAIL))

arch/powerpc/lib/sstep.c

2277

u = (word >> 20) & UPDATE;

arch/powerpc/lib/sstep.c

2282

u = word & UPDATE;

arch/powerpc/lib/sstep.c

2879

op->type = MKOP(LOAD, UPDATE, 8);

arch/powerpc/lib/sstep.c

2968

op->type = MKOP(STORE, UPDATE, 8);

arch/powerpc/lib/sstep.c

3117

if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {

arch/powerpc/lib/sstep.c

3493

if ((op->type & UPDATE) && size == sizeof(long) &&

arch/powerpc/lib/sstep.c

3562

if (op->type & UPDATE)

drivers/crypto/caam/caamalg_qi2.c

3148

flc = &ctx->flc[UPDATE];

drivers/crypto/caam/caamalg_qi2.c

3153

dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE],

drivers/crypto/caam/caamalg_qi2.c

3622

req_ctx->flc = &ctx->flc[UPDATE];

drivers/crypto/caam/caamalg_qi2.c

3623

req_ctx->flc_dma = ctx->flc_dma[UPDATE];

drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c

390

case UPDATE:

drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c

43

[UPDATE] = "update",

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

1021

entry->offset = i915_vma_offset(vma) | UPDATE;

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

1407

return target->node.start | UPDATE;

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

1587

offset = gen8_canonical_addr(offset & ~UPDATE);

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

3628

if (!(exec2_list[i].offset & UPDATE))

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

677

entry->offset = i915_vma_offset(vma) | UPDATE;

drivers/gpu/drm/nouveau/dispnv50/base507c.c

44

PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]);

drivers/gpu/drm/nouveau/dispnv50/core507d.c

49

PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

51

NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

52

NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

53

NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE),

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

69

PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

70

NVDEF(NVC37D, UPDATE, SPECIAL_HANDLING, NONE) |

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

71

NVDEF(NVC37D, UPDATE, INHIBIT_INTERRUPTS, FALSE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

44

PUSH_MTHD(push, NVCA7D, UPDATE,

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

45

NVDEF(NVCA7D, UPDATE, RELEASE_ELV, TRUE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

46

NVDEF(NVCA7D, UPDATE, SPECIAL_HANDLING, NONE) |

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

47

NVDEF(NVCA7D, UPDATE, INHIBIT_INTERRUPTS, FALSE));

drivers/gpu/drm/nouveau/dispnv50/curs507a.c

52

NVIF_WR32(user, NV507A, UPDATE,

drivers/gpu/drm/nouveau/dispnv50/curs507a.c

53

NVDEF(NV507A, UPDATE, INTERLOCK_WITH_CORE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/cursc37a.c

33

NVIF_WR32(user, NVC37A, UPDATE, 0x00000001);

drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c

40

PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 |

drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c

41

NVVAL(NVC37B, UPDATE, INTERLOCK_WITH_WINDOW,

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

282

PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 |

drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c

283

NVVAL(NVC37E, UPDATE, INTERLOCK_WITH_WIN_IMM,

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

102

#define REFFREQ_SEL(x) UPDATE(x, 11, 9)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

111

#define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

126

#define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

134

#define VS_CNT_THR_QST(x) UPDATE(x, 27, 20)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

136

#define HS_POL_QST(x) UPDATE(x, 19, 18)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

138

#define VS_POL_QST(x) UPDATE(x, 17, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

141

#define VS_FILTER_ORDER_QST(x) UPDATE(x, 1, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

148

#define I2C_SDA_OUT_HOLD_VALUE_QST(x) UPDATE(x, 15, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

150

#define I2C_SDA_IN_HOLD_VALUE_QST(x) UPDATE(x, 7, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

157

#define EESS_CTL_THR_QST(x) UPDATE(x, 19, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

159

#define OESS_CTL3_THR_QST(x) UPDATE(x, 11, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

161

#define EESS_OESS_SEL_QST(x) UPDATE(x, 5, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

164

#define KEY_DECRYPT_SEED_QST(x) UPDATE(x, 15, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

177

#define VPROC_FMT_OVR_VALUE(x) UPDATE(x, 6, 4)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

183

#define AFIFO_THR_LOW_QST(x) UPDATE(x, 25, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

185

#define AFIFO_THR_HIGH_QST(x) UPDATE(x, 9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

187

#define AFIFO_THR_MUTE_LOW_QST(x) UPDATE(x, 25, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

189

#define AFIFO_THR_MUTE_HIGH_QST(x) UPDATE(x, 9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

211

#define SCDC_SINKVERSION_QST(x) UPDATE(x, 7, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

221

#define CED_CHLOCKMAXER_QST(x) UPDATE(x, 14, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

271

#define UV_WID(x) UPDATE(x, 31, 28)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

273

#define Y_WID(x) UPDATE(x, 27, 24)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

275

#define DDR_STORE_FORMAT(x) UPDATE(x, 15, 12)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

295

#define LINE_FLAG_NUM(x) UPDATE(x, 31, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

297

#define LOCK_FRAME_NUM(x) UPDATE(x, 11, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

304

#define EDID_READ_EN(x) UPDATE(x, 8, 8)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

306

#define EDID_WRITE_EN(x) UPDATE(x, 7, 7)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

308

#define EDID_SLAVE_ADDR(x) UPDATE(x, 6, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

46

#define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

89

#define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

91

#define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9)

drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h

97

#define LDO_AFE_PROG(x) UPDATE(x, 24, 23)

drivers/net/wireless/ath/ath9k/beacon.c

486

if (sc->beacon.updateslot == UPDATE) {

drivers/net/wireless/ath/ath9k/htc_drv_main.c

1605

priv->beacon.updateslot = UPDATE;

drivers/net/wireless/ath/ath9k/main.c

1920

sc->beacon.updateslot = UPDATE;

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

111

#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

118

#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

121

#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

139

#define T_LPX_CNT(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

142

#define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

144

#define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

147

#define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

150

#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

153

#define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

156

#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

162

#define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

165

#define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

168

#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

171

#define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

173

#define T_TA_GO_CNT(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

176

#define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

178

#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

181

#define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

51

#define POWER_WORK_ENABLE UPDATE(1, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

52

#define POWER_WORK_DISABLE UPDATE(2, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

65

#define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

67

#define REG_PREDIV(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

70

#define REG_FBDIV_LO(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

73

#define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

75

#define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

78

#define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

80

#define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

83

#define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

85

#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

97

#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

101

#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

103

#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

105

#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

107

#define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

108

#define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

110

#define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

111

#define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

122

#define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

123

#define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

125

#define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

126

#define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

134

#define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

138

#define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

143

#define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

145

#define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

147

#define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

150

#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

152

#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

154

#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

158

#define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

160

#define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

164

#define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

166

#define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

174

#define RK3328_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

175

#define RK3328_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

177

#define RK3328_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

198

#define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

200

#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

202

#define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

203

#define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

204

#define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

205

#define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

221

#define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

223

#define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

225

#define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

36

#define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

38

#define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

53

#define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

55

#define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

57

#define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

59

#define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

63

#define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

65

#define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

68

#define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

70

#define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

73

#define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

75

#define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

77

#define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

81

#define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

83

#define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

85

#define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

88

#define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

90

#define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

95

#define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

96

#define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

97

#define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

98

#define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)

lib/zlib_inflate/inflate.c

712

UPDATE(state->check, put - out, out);

lib/zlib_inflate/inflate.c

755

UPDATE(state->check, strm->next_out - out, out);

lib/zlib_inflate/inflate.c

805

UPDATE(state->check, z->next_in, z->avail_in);