UINT64_CAST
UINT64_CAST(_pa) & NASID_MASK | \
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST(_pa) >> 3 & 0x1f << 4)
UINT64_CAST(_pa) & NASID_MASK | \
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST(_pa) >> 3 & 0x1f << 4)
UINT64_CAST(_pa) & NASID_MASK | \
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
UINT64_CAST(_pa) & NASID_MASK | \
UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
UINT64_CAST(_pa) >> 3 & 3)
#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
(UINT64_CAST(_ba) & 0x1f << 4) << 3)
#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
(UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
(UINT64_CAST(_ba) & 3) << 3)
#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
((UINT64_CAST(_pa) & ~NASID_MASK) | \
(UINT64_CAST(_nasid) << NASID_SHFT))
#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
(NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
#define SWIN_SIZE (UINT64_CAST 1 << 24)
#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
(UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
(NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
#define MMC_IO_PROT (UINT64_CAST 1 << 31)
#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
#define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
#define MRC_ENABLE (UINT64_CAST 1 << 63)
#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
#define MFC_VALID_MASK (UINT64_CAST 1 << 63)
#define MFC_VALID (UINT64_CAST 1 << 63)
#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
#define MLAN_DONE (UINT64_CAST 0x02)
#define MLAN_RD_DATA (UINT64_CAST 0x01)
#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
#define MSU_CORECLK (UINT64_CAST 1 << 6)
#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
#define MSU_NETSYNC (UINT64_CAST 1 << 5)
#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
#define MSU_I2CINTR (UINT64_CAST 1 << 3)
#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
#define MD_BANK_MASK (UINT64_CAST 7 << 29)
#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
#define MD_PROT_RW (UINT64_CAST 0x6)
#define MD_PROT_RO (UINT64_CAST 0x3)
#define MD_PROT_NO (UINT64_CAST 0x0)
#define MD_PROT_BAD (UINT64_CAST 0x5)
#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
#define NPROT_RESETOK (UINT64_CAST 1)
#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
#define NVP_TYPE_MASK (UINT64_CAST 0x3)
#define NVS_VALID (UINT64_CAST 1 << 63)
#define NVS_OVERRUN (UINT64_CAST 1 << 62)
#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
#define NVS_TYPE_MASK (UINT64_CAST 0x7)
#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
#define NAGE_AGE_MASK (UINT64_CAST 0xff)
#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
#define NPE_LINKRESET (UINT64_CAST 1 << 37)
#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
#define NPE_BADDEST (UINT64_CAST 1 << 34)
#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16)
#define PRLC_USE_INT (UINT64_CAST 1 << 16)
#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15)
#define PRLC_GCLK (UINT64_CAST 1 << 15)
#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8)
#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1)
#define PRLC_GCLK_EN_MASK (UINT64_CAST 1)
#define PRLC_GCLK_EN (UINT64_CAST 1)