arch/mips/mm/uasm-micromips.c

121

[insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-micromips.c

191

if (ip->fields & UIMM)

arch/mips/mm/uasm-micromips.c

46

[insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-micromips.c

95

[insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-mips.c

163

[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/mips/mm/uasm-mips.c

204

[insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/mips/mm/uasm-mips.c

257

if (ip->fields & UIMM)

arch/mips/mm/uasm-mips.c

54

[insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/powerpc/xmon/ppc-opc.c

3262

{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3267

{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},

arch/powerpc/xmon/ppc-opc.c

3268

{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3437

{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3438

{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3480

{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3481

{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3496

{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3497

{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3506

{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3507

{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

752

#define DCTL UIMM

arch/powerpc/xmon/ppc-opc.c

756

#define UIMM3 UIMM + 1