UDC_EP0OUT_IX
if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
if (ep->num != UDC_EP0OUT_IX)
&& ep->num != UDC_EP0OUT_IX)))
if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
dev->ep[UDC_EP0OUT_IX].in = 0;
tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
dev->ep[UDC_EP0OUT_IX].td->status |=
writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
&dev->ep[UDC_EP0OUT_IX].regs->subptr);
writel(dev->ep[UDC_EP0OUT_IX].td_phys,
&dev->ep[UDC_EP0OUT_IX].regs->desptr);
tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
dev->ep[UDC_EP0OUT_IX].naking = 0;
UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
dev->ep[UDC_EP0OUT_IX].ep.driver_data =
if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
dev->ep[UDC_EP0OUT_IX].naking = 0;
UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
dev->ep[UDC_EP0OUT_IX].num);
if (ep->num != UDC_EP0OUT_IX)
ep = &dev->ep[UDC_EP0OUT_IX];
tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
&dev->ep[UDC_EP0OUT_IX].regs->sts);
&dev->ep[UDC_EP0OUT_IX].regs->sts);
dev->ep[UDC_EP0OUT_IX].td_stp->data12;
dev->ep[UDC_EP0OUT_IX].td_stp->data34;
dev->ep[UDC_EP0OUT_IX].td_stp->status =
dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
&dev->ep[UDC_EP0OUT_IX].regs->desptr);
dev->ep[UDC_EP0OUT_IX].naking = 1;
tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
dev->ep[UDC_EP0OUT_IX].naking = 0;
UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
&dev->ep[UDC_EP0OUT_IX].regs->sts);
writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
dev->ep[UDC_EP0OUT_IX].td->status =
dev->ep[UDC_EP0OUT_IX].td->status,
ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
writel(dev->ep[UDC_EP0OUT_IX].td_phys,
&dev->ep[UDC_EP0OUT_IX].regs->desptr);
count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
dev->ep[UDC_EP0OUT_IX].td_phys);
dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
dev->ep[UDC_EP0OUT_IX].td_stp_dma);
&dev->ep[UDC_EP0OUT_IX].td_stp_dma);
dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
&dev->ep[UDC_EP0OUT_IX].td_phys);
dev->ep[UDC_EP0OUT_IX].td = td_data;
dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
dev->ep[UDC_EP0OUT_IX].td_stp_dma);
if (ep->num != UDC_EP0OUT_IX)
|| ep->num == UDC_EP0OUT_IX