UART_STAT
st = readl(port->membase + UART_STAT);
ret = readl(port->membase + UART_STAT);
writel(ret, port->membase + UART_STAT);
status = readl(port->membase + UART_STAT);
!(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL),
unsigned int st = readl(port->membase + UART_STAT);
unsigned int st = readl(port->membase + UART_STAT);
unsigned int st = readl(port->membase + UART_STAT);
ret = readl(port->membase + UART_STAT);
writel(ret, port->membase + UART_STAT);
unsigned int st = readl(port->membase + UART_STAT);
st = readl(port->membase + UART_STAT);
st = readl(port->membase + UART_STAT);
st = readl(port->membase + UART_STAT);
readl_poll_timeout_atomic(port->membase + UART_STAT, val,
readl_poll_timeout_atomic(port->membase + UART_STAT, val,
mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
writel(mvuart->pm_regs.stat, port->membase + UART_STAT);