UART_SCR
if (0 == readl(iomem_base + UART_SCR)) {
serial_out(up, UART_SCR, offset);
serial_out(up, UART_SCR, offset);
serial_out(up, UART_SCR, canary);
if (serial_in(up, UART_SCR) == canary)
case UART_SCR:
case UART_SCR: /* SCR @ 0x20 (+1) */
case UART_SCR: /* SCR @ 0x20 (+1) */
#define KUART_EMODE_ICR_OFFSET UART_SCR
serial_out(up, UART_SCR, UART_CPR);
val = inb(base + UART_SCR);
inb(base + UART_SCR);
outb(qopr, base + UART_SCR);
val = inb(base + UART_SCR);
outb(val | 0x10, base + UART_SCR);
outb(val, base + UART_SCR);
val = inb(base + UART_SCR);
outb(val | 0x10, base + UART_SCR);
outb(val, base + UART_SCR);
val = inb(base + UART_SCR);
if (!(inb(UART_SCR) & 0x20)) {
readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
serial_in(up, UART_SCR);
if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
scratch = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0xa5);
status1 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0x5a);
status2 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, scratch);
case UART_SCR:
case UART_SCR:
tegra_uart_read(tup, UART_SCR);
tegra_uart_read(tup, UART_SCR);
tegra_uart_read(tup, UART_SCR);
scratch = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0xa5);
status1 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0x5a);
status2 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, scratch);
serial_out(up, UART_SCR, offset);
case UART_SCR:
case UART_SCR:
outb(0xaa, io_base + UART_SCR);
c = inb(io_base + UART_SCR);
outb(0x55, io_base + UART_SCR);
c = inb(io_base + UART_SCR);