UART_LSR_DR
while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
while (in_8(avr_addr + UART_LSR) & UART_LSR_DR)
while (inb_p(speakup_info.port_tts + UART_LSR) & UART_LSR_DR) {
while (!(inb_p(speakup_info.port_tts + UART_LSR) & UART_LSR_DR)) {
if (!(lsr & UART_LSR_DR))
} while (inb(iobase + UART_LSR) & UART_LSR_DR);
port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
port->ignore_status_mask |= UART_LSR_DR;
port->read_status_mask &= ~UART_LSR_DR;
} while ((*status & UART_LSR_DR) && (max_count-- > 0));
if (lsr & UART_LSR_DR)
state->read_status_mask &= ~UART_LSR_DR;
status = UART_LSR_DR; /* We obviously have a character! */
info->read_status_mask = UART_LSR_OE | UART_LSR_DR;
info->ignore_status_mask |= UART_LSR_DR;
} while (status & UART_LSR_DR);
if (status & UART_LSR_DR)
info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (lsr & (UART_LSR_DR | UART_LSR_BI)) {
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
if ((status & UART_LSR_DR) == 0) {
if ((status & UART_LSR_DR) == 0) {
if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR))
if (lsr & UART_LSR_DR) {
if (!(status & (UART_LSR_DR | UART_LSR_BI)))
if (status & (UART_LSR_DR | UART_LSR_BI)) {
if (!(status & UART_LSR_DR))
if ((lsr & (UART_LSR_DR | UART_LSR_BI)) &&
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
port->ignore_status_mask |= UART_LSR_DR;
if (likely(lsr & UART_LSR_DR))
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
if (!(lsr & UART_LSR_DR))
port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
port->ignore_status_mask |= UART_LSR_DR;
for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
if (!(linestatus & UART_LSR_DR))
if (!(linestatus & UART_LSR_DR)) {
linestatus &= ~UART_LSR_DR;
if (ch->ch_cached_lsr & UART_LSR_DR) {
if (!(status & UART_LSR_DR)) {
(UART_LSR_THRE | UART_LSR_DR))) {
up->port.read_status_mask &= ~UART_LSR_DR;
if (likely(lsr & UART_LSR_DR)) {
if (!(lsr & UART_LSR_DR))
if (serial_in(up, UART_LSR) & UART_LSR_DR)
if (serial_in(up, UART_LSR) & UART_LSR_DR)
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
up->port.ignore_status_mask |= UART_LSR_DR;
if (!(lsr & UART_LSR_DR))
i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
} while ((*status & UART_LSR_DR) && (max_count-- > 0));
if (lsr & UART_LSR_DR)
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
up->port.ignore_status_mask |= UART_LSR_DR;
while (!(lsr & UART_LSR_DR))
up->port.read_status_mask &= ~UART_LSR_DR;
tup->uport.ignore_status_mask |= UART_LSR_DR;
if ((lsr & UART_LSR_TEMT) && !(lsr & UART_LSR_DR))
if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
if (!(lsr & UART_LSR_DR))
if (tup->uport.ignore_status_mask & UART_LSR_DR)
if (tup->uport.ignore_status_mask & UART_LSR_DR)
up->port.read_status_mask &= ~UART_LSR_DR;
} while ((*status & UART_LSR_DR) && (max_count-- > 0));
if (status & UART_LSR_DR)
} while (serial_in(up, UART_LSR) & UART_LSR_DR);
if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
up->port.ignore_status_mask |= UART_LSR_DR;
lsr |= UART_LSR_DR;
while ((status = inb(uart->base + UART_LSR)) & UART_LSR_DR) {