TxINT_ENAB
cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */
or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */
or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
if (txint & TxINT_ENAB) {
zport->regs[1] = txint & ~TxINT_ENAB;
if (txint & TxINT_ENAB) {
zport->regs[1] |= TxINT_ENAB;
zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;