Symbol: BLKADDR_RVUM
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
109
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
115
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
123
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
128
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
169
otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
171
otx2_cpt_write64(pf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
187
intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
198
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
201
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
219
intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
226
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
229
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
27
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
29
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
34
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
41
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
417
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT_ENA_W1C,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
420
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT, 0x1ULL);
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
439
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT, 0x1ULL);
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
441
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT_ENA_W1S,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
53
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
55
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
577
rev = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
578
RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
58
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
614
cfg = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
65
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
76
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0),
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
80
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
83
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFME_INTX(0),
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
86
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
92
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(1),
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
94
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
97
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFME_INTX(1),
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
99
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
354
intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
363
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM,
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
426
intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT);
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
443
otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT,
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
16
otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
20
otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
27
otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
31
otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
56
intr = otx2_cpt_read64(cptvf->reg_base, BLKADDR_RVUM, 0,
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
63
otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
109
intr = rvu_read64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status);
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
110
rvu_write64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status, intr);
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
130
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
133
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
136
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
139
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
143
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1S(0),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
146
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1S(1),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
149
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1S(0),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
152
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1S(1),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
158
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1C(0),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
161
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF_INT_ENA_W1C(1),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
164
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1C(0),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
167
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFAF1_INT_ENA_W1C(1),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
297
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_AF_PFX_ADDR(pf),
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
328
rvu_write64(rvu, BLKADDR_RVUM, RVU_MBOX_PF_VF_CFG, ilog2(MBOX_SIZE));
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
331
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
401
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_NIXX_CFG(0) |
drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c
3478
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
1374
for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2094
cfg = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2522
bar4 = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2546
bar4 = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2549
bar4 = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2601
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2780
intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2782
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2832
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2836
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2956
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2966
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
2969
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3002
intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3009
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3012
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3051
intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3069
intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
307
cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3077
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3080
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3096
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3102
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3106
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3126
offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
315
cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3209
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3212
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3229
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
323
cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3232
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3235
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3242
pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
331
cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3363
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
3364
rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
401
rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
409
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
425
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
453
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
465
if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
490
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
497
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
612
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
621
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
646
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
650
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
657
cfg = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
677
cfg = rvu_read64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
682
rvu_write64(rvu, BLKADDR_RVUM,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
692
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
697
phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
706
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
739
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
775
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
960
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
105
pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18;
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
85
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
89
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
91
err = rvu_poll_reg(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS, BIT_ULL(0), false);
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
96
val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS);
drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
3258
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
3654
cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
704
blkaddr = BLKADDR_RVUM;
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
2990
rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));