arch/mips/include/asm/txx9/tx4927.h

42

#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)

arch/mips/include/asm/txx9/tx4927.h

43

#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)

arch/mips/include/asm/txx9/tx4927.h

44

#define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)

arch/mips/include/asm/txx9/tx4927.h

45

#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)

arch/mips/include/asm/txx9/tx4927.h

46

#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)

arch/mips/include/asm/txx9/tx4927.h

47

#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)

arch/mips/include/asm/txx9/tx4927.h

49

#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)

arch/mips/include/asm/txx9/tx4927.h

51

#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)

arch/mips/include/asm/txx9/tx4927.h

52

#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)

arch/mips/include/asm/txx9/tx4927.h

53

#define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)

arch/mips/txx9/generic/setup_tx4927.c

95

txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,