arch/alpha/kernel/core_tsunami.c

227

TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */

arch/alpha/kernel/core_tsunami.c

231

if (TSUNAMI_cchip->misc.csr & (1L << 28)) {

arch/alpha/kernel/core_tsunami.c

232

int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;

arch/alpha/kernel/core_tsunami.c

233

TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */

arch/alpha/kernel/core_tsunami.c

387

tmp = (unsigned long)(TSUNAMI_cchip - 1);

arch/alpha/kernel/core_tsunami.c

396

printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);

arch/alpha/kernel/core_tsunami.c

397

printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr);

arch/alpha/kernel/core_tsunami.c

398

printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);

arch/alpha/kernel/core_tsunami.c

399

printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);

arch/alpha/kernel/core_tsunami.c

400

printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);

arch/alpha/kernel/core_tsunami.c

401

printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);

arch/alpha/kernel/core_tsunami.c

402

printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);

arch/alpha/kernel/core_tsunami.c

403

printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);

arch/alpha/kernel/core_tsunami.c

417

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/core_tsunami.c

448

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/core_tsunami.c

467

if (TSUNAMI_cchip->csc.csr & 1L<<14)

arch/alpha/kernel/sys_dp264.c

197

pld = TSUNAMI_cchip->dir0.csr;

arch/alpha/kernel/sys_dp264.c

49

register tsunami_cchip *cchip = TSUNAMI_cchip;