TSR
[TSR] = 5,
sh_mtu2_read(ch, TSR);
sh_mtu2_write(ch, TSR, ~TSR_TGFA);
volatile u_char TSR; /* Timer Status Register */
bp, TSR);
macb_writel(bp, TSR, macb_readl(bp, TSR));
macb_writel(bp, TSR, -1);
regs_buff[3] = macb_readl(bp, TSR);
if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
macb_writel(bp, TSR, -1);
data = ioread32(ioaddr + TSR);
count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
if (td->tdesc0.TSR & TSR0_TERR) {
if (td->tdesc0.TSR & TSR0_CDH)
if (td->tdesc0.TSR & TSR0_CRS)
if (td->tdesc0.TSR & TSR0_ABT)
if (td->tdesc0.TSR & TSR0_OWC)
__le16 TSR; /* Transmit status register */
u_long TSR ; /* timer */
smc->srf.TSR = smt_get_time() ;
tsr = smt_get_time() - smc->srf.TSR ;
smc->srf.TSR = smt_get_time() ;
smc->srf.TSR = smt_get_time() ;
smc->srf.TSR = smt_get_time() ;
smc->srf.TSR = smt_get_time() ;
smc->srf.TSR = smt_get_time() ;
smc->srf.TSR = smt_get_time() ;