drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

63

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

135

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

151

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

174

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

92

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1074

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

153

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

666

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

781

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

886

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

915

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

961

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

126

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

285

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

980

kfree(TO_DCN401_DPP(*dpp));