TRCVMIDCCTLR1
((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
CASE_##op((val), TRCVMIDCCTLR1) \