TRCCIDCCTLR0
((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
CHECKREG(TRCCIDCCTLR0, ctxid_mask0);
state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
CASE_##op((val), TRCCIDCCTLR0) \