drivers/gpu/drm/gma500/cdv_device.c

125

blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/cdv_device.c

126

REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |

drivers/gpu/drm/gma500/cdv_device.c

256

regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_device.c

333

REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_device.c

77

u32 max = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_device.c

95

u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

239

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

67

retval = ((REG_READ(BLC_PWM_CTL) &

drivers/gpu/drm/gma500/cdv_intel_lvds.c

92

REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/cdv_intel_lvds.c

93

REG_WRITE(BLC_PWM_CTL,

drivers/gpu/drm/gma500/oaktrail_device.c

101

REG_WRITE(BLC_PWM_CTL, value | (value << 16));

drivers/gpu/drm/gma500/oaktrail_device.c

178

regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);

drivers/gpu/drm/gma500/oaktrail_device.c

308

PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);

drivers/gpu/drm/gma500/oaktrail_device.c

53

max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;

drivers/gpu/drm/gma500/oaktrail_device.c

70

REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);

drivers/gpu/drm/gma500/oaktrail_lvds.c

166

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/oaktrail_lvds.c

179

ret = ((REG_READ(BLC_PWM_CTL) &

drivers/gpu/drm/gma500/psb_device.c

71

REG_WRITE(BLC_PWM_CTL,

drivers/gpu/drm/gma500/psb_intel_lvds.c

148

REG_WRITE(BLC_PWM_CTL,

drivers/gpu/drm/gma500/psb_intel_lvds.c

190

blc_pwm_ctl = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

192

REG_WRITE(BLC_PWM_CTL,

drivers/gpu/drm/gma500/psb_intel_lvds.c

268

lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

309

REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

434

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

68

ret = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

80

REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1327

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1373

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

170

val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

258

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

drivers/gpu/drm/i915/display/intel_backlight.c

259

intel_de_write(display, BLC_PWM_CTL, tmp | level);

drivers/gpu/drm/i915/display/intel_backlight.c

578

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

583

intel_de_write(display, BLC_PWM_CTL, 0);

drivers/gpu/drm/i915/display/intel_backlight.c

596

intel_de_write(display, BLC_PWM_CTL, ctl);

drivers/gpu/drm/i915/display/intel_backlight.c

597

intel_de_posting_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

634

intel_de_write(display, BLC_PWM_CTL, ctl);