arch/arm64/include/asm/kvm_arm.h

54

#define HCR_TPU __HCR(TPU)

arch/sh/kernel/cpu/sh3/setup-sh7720.c

257

INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

258

INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

259

INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

274

{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

344

INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

403

{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

418

{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

560

INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

617

{ 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

634

{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1050

0, TPU, 0, TSIF } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

1073

{ 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

925

INTC_VECT(TPU, 0x9A0),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

281

INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

310

PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

328

{ 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },

drivers/gpu/drm/radeon/r600_dpm.c

375

WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);

drivers/perf/hisilicon/hns3_pmu.c

554

HNS3_PMU_DLY_EVT_PAIR(dly_tpu, TPU),

drivers/perf/hisilicon/hns3_pmu.c

621

HNS3_PMU_DLY_FLT_MODE_PAIR(dly_tpu, TPU),