drivers/clocksource/timer-stm32.c

114

writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);

drivers/counter/stm32-timer-cnt.c

143

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/counter/stm32-timer-cnt.c

151

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);

drivers/counter/stm32-timer-cnt.c

206

*enable = cr1 & TIM_CR1_CEN;

drivers/counter/stm32-timer-cnt.c

220

if (!(cr1 & TIM_CR1_CEN)) {

drivers/counter/stm32-timer-cnt.c

228

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,

drivers/counter/stm32-timer-cnt.c

229

TIM_CR1_CEN);

drivers/counter/stm32-timer-cnt.c

232

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/counter/stm32-timer-cnt.c

233

if (cr1 & TIM_CR1_CEN)

drivers/counter/stm32-timer-cnt.c

810

regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

drivers/iio/trigger/stm32-timer-trigger.c

180

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

197

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

253

if (cr1 & TIM_CR1_CEN) {

drivers/iio/trigger/stm32-timer-trigger.c

465

*val = (dat & TIM_CR1_CEN) ? 1 : 0;

drivers/iio/trigger/stm32-timer-trigger.c

509

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

511

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

835

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/iio/trigger/stm32-timer-trigger.c

856

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

379

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

403

ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

468

regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

drivers/pwm/pwm-stm32.c

513

regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);