TIMER_CTRL
writel_relaxed(0, base + TIMER_CTRL);
writel_relaxed(0, base + TIMER_CTRL);
writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
clockevent_mps2_writel(0, ce, TIMER_CTRL);
clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
writel(ctrl, clkevt_base + TIMER_CTRL);
writel(0, base + TIMER_CTRL);
writel(ctrl, base + TIMER_CTRL);
u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
writel(ctrl, clkevt_base + TIMER_CTRL);
u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
writel(ctrl, clkevt_base + TIMER_CTRL);
u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
writel(ctrl, clkevt_base + TIMER_CTRL);
writel(ctrl, clkevt_base + TIMER_CTRL);
atomic_io_modify(timer_base + TIMER_CTRL,
atomic_io_modify(timer_base + TIMER_CTRL,
atomic_io_modify(timer_base + TIMER_CTRL,
atomic_io_modify(timer_base + TIMER_CTRL,
.ctrl = TIMER_CTRL,
val = readl(airoha_wdt->base + TIMER_CTRL);
writel(val, airoha_wdt->base + TIMER_CTRL);
val = readl(airoha_wdt->base + TIMER_CTRL);
writel(val, airoha_wdt->base + TIMER_CTRL);
atomic_io_modify(dev->reg + TIMER_CTRL,
atomic_io_modify(dev->reg + TIMER_CTRL,
atomic_io_modify(dev->reg + TIMER_CTRL,
atomic_io_modify(dev->reg + TIMER_CTRL, val, val);
atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg);
atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg);
atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0);
atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0);
running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;