BIT_U32
#define BDB_263_VBT_EDP_LINK_RATE_1_62 BIT_U32(0)
#define BDB_263_VBT_EDP_LINK_RATE_2_16 BIT_U32(1)
#define BDB_263_VBT_EDP_LINK_RATE_2_43 BIT_U32(2)
#define BDB_263_VBT_EDP_LINK_RATE_2_7 BIT_U32(3)
#define BDB_263_VBT_EDP_LINK_RATE_3_24 BIT_U32(4)
#define BDB_263_VBT_EDP_LINK_RATE_4_32 BIT_U32(5)
#define BDB_263_VBT_EDP_LINK_RATE_5_4 BIT_U32(6)
#define BDB_263_VBT_EDP_LINK_RATE_6_75 BIT_U32(7)
#define BDB_263_VBT_EDP_LINK_RATE_8_1 BIT_U32(8)
#define BDB_263_VBT_EDP_LINK_RATE_10 BIT_U32(9)
#define BDB_263_VBT_EDP_LINK_RATE_13_5 BIT_U32(10)
#define BDB_263_VBT_EDP_LINK_RATE_20 BIT_U32(11)
#define REG_BIT(n) BIT_U32(n)
#define RXPIER_AXIERR BIT_U32(22)
#define RXPIER_CRCERR BIT_U32(21)
#define RXPIER_WCERR BIT_U32(20)
#define RXPIER_UEXDTERR BIT_U32(19)
#define RXPIER_UEXPKTERR BIT_U32(18)
#define RXPIER_ECCERR BIT_U32(17)
#define RXPIER_MLFERR BIT_U32(16)
#define RXPIER_RCVACK BIT_U32(14)
#define RXPIER_RCVEOT BIT_U32(10)
#define RXPIER_RCVAKE BIT_U32(9)
#define RXPIER_RCVRESP BIT_U32(8)
#define RXPIER_BTAREQEND BIT_U32(0)
#define RXPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
#define LINKSR_LPBUSY BIT_U32(1)
#define LINKSR_HSBUSY BIT_U32(0)
#define TOSR_TATO BIT_U32(2)
#define TOSR_LRXHTO BIT_U32(1)
#define TOSR_HRXTO BIT_U32(0)
#define TOSCR_TATO BIT_U32(2)
#define TOSCR_LRXHTO BIT_U32(1)
#define TOSCR_HRXTO BIT_U32(0)
#define TXVMSETR_SYNSEQ_EVENTS BIT_U32(16) /* 0:Pulses 1:Events */
#define TXVMSETR_VSTPM BIT_U32(15)
#define TXVMSETR_PIXWDTH BIT_U32(8) /* Only allowed value */
#define TXVMSETR_VSEN BIT_U32(4)
#define TXVMSETR_HFPBPEN BIT_U32(2)
#define TXVMSETR_HBPBPEN BIT_U32(1)
#define TXVMSETR_HSABPEN BIT_U32(0)
#define TXVMCR_VFCLR BIT_U32(12)
#define TXVMCR_EN_VIDEO BIT_U32(0)
#define TXVMSR_STR BIT_U32(16)
#define TXVMSR_VFRDY BIT_U32(12)
#define TXVMSR_ACT BIT_U32(8)
#define TXVMSR_RDY BIT_U32(0)
#define TXVMSCR_STR BIT_U32(16)
#define TXVMVPRMSET0R_HSPOL_LOW BIT_U32(17) /* 0:High 1:Low */
#define TXVMVPRMSET0R_VSPOL_LOW BIT_U32(16) /* 0:High 1:Low */
#define TXVMVPRMSET0R_CSPC_YCbCr BIT_U32(4) /* 0:RGB 1:YCbCr */
#define PPISETR_CLEN BIT_U32(8)
#define PPICLCR_TXREQHS BIT_U32(8)
#define PPICLCR_TXULPSEXT BIT_U32(1)
#define TXCMSETR_SPDTYP BIT_U32(8) /* 0:HS 1:LP */
#define PPICLCR_TXULPSCLK BIT_U32(0)
#define PPICLSR_HSTOLP BIT_U32(27)
#define PPICLSR_TOHS BIT_U32(26)
#define PPICLSR_STPST BIT_U32(0)
#define PPICLSCR_HSTOLP BIT_U32(27)
#define PPICLSCR_TOHS BIT_U32(26)
#define TXCMSETR_LPPDACC BIT_U32(0)
#define PPIDL0SR_DIR BIT_U32(10)
#define PPIDL0SR_STPST BIT_U32(6)
#define LPCLKSET_CKEN BIT_U32(8)
#define CFGCLKSET_CKEN BIT_U32(8)
#define TXCMCR_BTATYP BIT_U32(2)
#define DOTCLKDIV_CKEN BIT_U32(8)
#define VCLKSET_CKEN BIT_U32(16)
#define VCLKSET_COLOR_YCC BIT_U32(8) /* 0:RGB 1:YCbCr */
#define TXCMCR_BTAREQ BIT_U32(1)
#define VCLKEN_CKEN BIT_U32(0)
#define TXCMCR_TXREQ BIT_U32(0)
#define PHYSETUP_SHUTDOWNZ BIT_U32(1)
#define PHYSETUP_RSTZ BIT_U32(0)
#define CLOCKSET1_LOCK_PHY BIT_U32(17)
#define CLOCKSET1_CLKSEL BIT_U32(8)
#define CLOCKSET1_SHADOW_CLEAR BIT_U32(1)
#define CLOCKSET1_UPDATEPLL BIT_U32(0)
#define TXCMSR_CLSNERR BIT_U32(18)
#define TXCMSR_AXIERR BIT_U32(16)
#define PHTW_DWEN BIT_U32(24)
#define PHTW_CWEN BIT_U32(8)
#define TXCMSR_TXREQEND BIT_U32(0)
#define PHTR_TESTDOUT_TEST BIT_U32(16)
#define PHTC_TESTCLR BIT_U32(0)
#define TXCMSCR_CLSNERR BIT_U32(18)
#define TXCMSCR_AXIERR BIT_U32(16)
#define TXCMSCR_TXREQEND BIT_U32(0)
#define TXCMIER_CLSNERR BIT_U32(18)
#define TXCMIER_AXIERR BIT_U32(16)
#define TXCMIER_TXREQEND BIT_U32(0)
#define TXCMPHDR_FMT BIT_U32(24) /* 0:SP 1:LP */
#define RXPSETR_LPPDACC BIT_U32(0)
#define RXPSR_ECCERR1B BIT_U32(28)
#define RXPSR_UEXTRGERR BIT_U32(25)
#define RXPSR_RESPTOERR BIT_U32(24)
#define RXPSR_OVRERR BIT_U32(23)
#define RXPSR_AXIERR BIT_U32(22)
#define RXPSR_CRCERR BIT_U32(21)
#define RXPSR_WCERR BIT_U32(20)
#define RXPSR_UEXDTERR BIT_U32(19)
#define RXPSR_UEXPKTERR BIT_U32(18)
#define RXPSR_ECCERR BIT_U32(17)
#define RXPSR_MLFERR BIT_U32(16)
#define RXPSR_RCVACK BIT_U32(14)
#define RXPSR_RCVEOT BIT_U32(10)
#define RXPSR_RCVAKE BIT_U32(9)
#define RXPSR_RCVRESP BIT_U32(8)
#define RXPSR_BTAREQEND BIT_U32(0)
#define RXPSCR_ECCERR1B BIT_U32(28)
#define RXPSCR_UEXTRGERR BIT_U32(25)
#define RXPSCR_RESPTOERR BIT_U32(24)
#define RXPSCR_OVRERR BIT_U32(23)
#define RXPSCR_AXIERR BIT_U32(22)
#define RXPSCR_CRCERR BIT_U32(21)
#define RXPSCR_WCERR BIT_U32(20)
#define RXPSCR_UEXDTERR BIT_U32(19)
#define RXPSCR_UEXPKTERR BIT_U32(18)
#define RXPSCR_ECCERR BIT_U32(17)
#define RXPSCR_MLFERR BIT_U32(16)
#define RXPSCR_RCVACK BIT_U32(14)
#define RXPSCR_RCVEOT BIT_U32(10)
#define RXPSCR_RCVAKE BIT_U32(9)
#define RXPSCR_RCVRESP BIT_U32(8)
#define RXPSCR_BTAREQEND BIT_U32(0)
#define RXPIER_ECCERR1B BIT_U32(28)
#define RXPIER_UEXTRGERR BIT_U32(25)
#define RXPIER_RESPTOERR BIT_U32(24)
#define RXPIER_OVRERR BIT_U32(23)
mbx_mask = ~BIT_U32(HECC_RX_LAST_MBOX);
queue_mask = BIT_U32(bp->num_queues) - 1;
queue_mask = BIT_U32(bp->num_queues) - 1;
#define GMAC_AN_CTRL_RAN BIT_U32(9) /* Restart Auto-Negotiation */
#define GMAC_AN_CTRL_ANE BIT_U32(12) /* Auto-Negotiation Enable */
#define GMAC_AN_CTRL_ELE BIT_U32(14) /* External Loopback Enable */
#define GMAC_AN_CTRL_ECD BIT_U32(16) /* Enable Comma Detect */
#define GMAC_AN_CTRL_LR BIT_U32(17) /* Lock to Reference */
#define GMAC_AN_CTRL_SGMRAL BIT_U32(18) /* SGMII RAL Control */
eint_wake_mask_values[wakeup_reg] |= BIT_U32(shift);
eint_wake_mask_values[wakeup_reg] &= ~BIT_U32(shift);
static_assert(assert_type(u32, BIT_U32(0)) == 1u);
static_assert(assert_type(u32, BIT_U32(31)) == 0x80000000u);
return BIT_U32(i);
#define QUIRK_FLAG(x) BIT_U32(QUIRK_TYPE_ ## x)