drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

63

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

135

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

151

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

174

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

95

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1052

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

153

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

660

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

775

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

880

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

909

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

955

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

944

kfree(TO_DCN401_DPP(*dpp));