TG3_FL_NOT_5705
{ MAC_MODE, TG3_FL_NOT_5705,
{ MAC_STATUS, TG3_FL_NOT_5705,
{ MAC_RX_MODE, TG3_FL_NOT_5705,
{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
{ HOSTCC_MODE, TG3_FL_NOT_5705,
{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))