arch/sh/kernel/cpu/sh3/setup-sh7705.c

48

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),

arch/sh/kernel/cpu/sh3/setup-sh7705.c

56

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh770x.c

37

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),

arch/sh/kernel/cpu/sh3/setup-sh770x.c

68

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh7710.c

50

INTC_VECT(TMU2, 0x440),

arch/sh/kernel/cpu/sh3/setup-sh7710.c

58

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh7720.c

239

INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

267

{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh4/setup-sh7750.c

194

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),

arch/sh/kernel/cpu/sh4/setup-sh7750.c

206

{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh4/setup-sh7760.c

104

{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4/setup-sh7760.c

73

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

363

INTC_VECT(TMU2, 0x440),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

388

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

409

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

301

INTC_VECT(TMU2, 0x440),

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

325

{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

346

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

576

INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

602

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

623

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

1064

{ INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

851

INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

949

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

257

INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

297

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

316

TMU2, TMU2_TICPI } },

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

360

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

407

INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

444

{ TMU1, TMU2, TMU2_TICPI, TMU3 } },

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

319

INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

351

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

365

TMU2, TMU2_TICPI } },

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

395

INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

434

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

463

TMU2, TMU2_TICPI } },

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

509

INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

582

TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

619

{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },

arch/sh/kernel/cpu/sh4a/setup-shx3.c

198

INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),

arch/sh/kernel/cpu/sh4a/setup-shx3.c

269

0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },

arch/sh/kernel/cpu/sh4a/setup-shx3.c

292

TMU3, TMU2, TMU1, TMU0 } },