arch/sh/kernel/cpu/sh3/setup-sh7705.c

47

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh3/setup-sh7705.c

56

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh770x.c

36

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh3/setup-sh770x.c

68

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh7710.c

49

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh3/setup-sh7710.c

58

{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh3/setup-sh7720.c

238

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh3/setup-sh7720.c

267

{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh4/setup-sh7750.c

193

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4/setup-sh7750.c

206

{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },

arch/sh/kernel/cpu/sh4/setup-sh7760.c

104

{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4/setup-sh7760.c

72

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

362

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

388

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

409

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

300

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

325

{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

346

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

575

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

602

{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

623

{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

1064

{ INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

850

INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),

arch/sh/kernel/cpu/sh4a/setup-sh7757.c

949

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

256

INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

297

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

315

{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

359

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

407

INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

429

{ 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

318

INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

351

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

364

{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

394

INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

434

INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

462

{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,

arch/sh/kernel/cpu/sh4a/setup-shx3.c

197

INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),

arch/sh/kernel/cpu/sh4a/setup-shx3.c

269

0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },

arch/sh/kernel/cpu/sh4a/setup-shx3.c

292

TMU3, TMU2, TMU1, TMU0 } },