drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

510

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

513

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

520

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

523

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

285

SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

293

SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

302

SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

312

SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

479

uint8_t TMDS_PIXEL_ENCODING;

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h

612

uint32_t TMDS_PIXEL_ENCODING;

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

470

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

473

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

278

SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

494

type TMDS_PIXEL_ENCODING;\

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

172

SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

170

SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h

91

SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

221

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

224

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

171

SE_SF(DIG0_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

849

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

852

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

93

SE_SF(DIG1_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\