arch/powerpc/mm/book3s64/radix_tlb.c

1032

WARN_ON_ONCE(end == TLB_FLUSH_ALL);

arch/powerpc/mm/book3s64/radix_tlb.c

1250

WARN_ON_ONCE(end == TLB_FLUSH_ALL);

arch/x86/hyperv/mmu.c

144

if (info->end == TLB_FLUSH_ALL) {

arch/x86/hyperv/mmu.c

218

if (info->end == TLB_FLUSH_ALL) {

arch/x86/include/asm/tlb.h

15

unsigned long start = 0UL, end = TLB_FLUSH_ALL;

arch/x86/include/asm/tlbflush.h

307

flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)

arch/x86/mm/pat/set_memory.c

451

end = TLB_FLUSH_ALL;

arch/x86/mm/tlb.c

1257

if (f->end != TLB_FLUSH_ALL &&

arch/x86/mm/tlb.c

1279

nr_invalidate = TLB_FLUSH_ALL;

arch/x86/mm/tlb.c

1356

if (info->end == TLB_FLUSH_ALL)

arch/x86/mm/tlb.c

1357

trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);

arch/x86/mm/tlb.c

1425

end = TLB_FLUSH_ALL;

arch/x86/mm/tlb.c

1558

if (info->end == TLB_FLUSH_ALL)

arch/x86/mm/tlb.c

1735

info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,

arch/x86/mm/tlb.c

513

if (info->end == TLB_FLUSH_ALL) {

arch/x86/mm/tlb.c

953

trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);

arch/x86/xen/mmu_pv.c

1353

if (info->end != TLB_FLUSH_ALL &&

mm/pgtable-generic.c

434

iommu_sva_invalidate_kva_range(PAGE_OFFSET, TLB_FLUSH_ALL);