TI_CLK_MUX
{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
{ 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
{ 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
{ 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
{ 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
{ 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
{ 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
case TI_CLK_MUX: