TI_CLK_GATE
{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
{ 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
{ 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
{ 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
{ 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
{ 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
case TI_CLK_GATE: