BIT6
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
real_byte5 &= ~BIT6;
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
real_byte5 &= ~BIT6;
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define ALGO_TRACE_FW_EXEC BIT6
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
#define DATAIN BIT6
#define EN_ATN_STOP BIT6
#define LPFC_SLI4_INTR6 BIT6
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
BIT5 + BIT6 + BIT7);
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);