BIT5
#define BT_INFO_8192E_2ANT_B_HID BIT5
if ((byte1 & BIT4) && !(byte1 & BIT5)) {
real_byte1 |= BIT5;
real_byte5 |= BIT5;
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_HID BIT5
if (byte1 & BIT4 && !(byte1 & BIT5)) {
real_byte1 |= BIT5;
real_byte5 |= BIT5;
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define ALGO_TRACE_FW_DETAIL BIT5
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
#define SRB_ERROR BIT5
#define RESIDUAL_VALID BIT5
#define EN_TAG_QUEUEING BIT5
#define LUN_CHECK BIT5
#define LPFC_SLI4_INTR5 BIT5
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
BIT5 + BIT6 + BIT7);
viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
(viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 |
reg_val << 4, BIT5);