BIT4
u8tmp |= BIT4;
if (!(coex_sta->bt_info_ext & BIT4))
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
if (coex_sta->bt_info_ext & BIT4) {
if ((byte1 & BIT4) && !(byte1 & BIT5)) {
real_byte1 &= ~BIT4;
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
if (!(coex_sta->bt_info_ext & BIT4))
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
if (byte1 & BIT4 && !(byte1 & BIT5)) {
real_byte1 &= ~BIT4;
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
#define WIFI_P2P_GC_CONNECTED BIT4
#define ALGO_TRACE_FW BIT4
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
#define PARITY_ERROR BIT4
#define ENABLE_TIMER BIT4
#define WIDE_NEGO_STATE BIT4
#define NO_SEEK BIT4
#define LPFC_SLI4_INTR4 BIT4
viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
BIT4);
viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
bdual = BIT4;
viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
(viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 |
reg_val << 3, BIT4);