BIT3
if ((coex_sta->bt_info_ext & BIT3)) {
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
if (coex_sta->bt_info_ext & BIT3) {
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
if ((coex_sta->bt_info_ext & BIT3)) {
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
if ((coex_sta->bt_info_ext & BIT3) && !wifi_under_5g) {
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define WIFI_P2P_GO_CONNECTED BIT3
#define ALGO_TRACE BIT3
#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
#define UNDER_RUN BIT3
#define WIDE_NEGO_DONE BIT3
#define ACTIVE_NEGATION BIT3
#define UNIT_RETRY BIT3
#define LPFC_SLI4_INTR3 BIT3
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);